ASX340AT datasheet(37/54 Pages) ONSEMI

37 / 54 page

ASX340AT

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The image flow pipeline typically generates up to 16 bits

per pixel − for example, YCbCr or 565RGB − but has only

an 8-bit port through which to communicate this pixel data.

To generate NTSC or PAL format images, the sensor core

requires a 27 MHz clock.

10 bits/pixel

1 pixel/clock

16 bits/pixel

1 pixel/clock

16 bits/pixel (TYP)

0.5 pixel/clock

Colorpipe

Output Interface

EXTCLK

Sensor Core

Sensor

Pixel Clock

Sensor

Master Clock

Figure 37. Primary Clock Relationships

Floating Inputs

The following ASX340AT pins cannot be floated:

• SDATA–This pin is bidirectional and should not be

floated

• FRAME_SYNC

• TRST_N

• SCLK

• SADDR

• ATEST1

• ATEST2

Output Data Ordering

TABLE 29. EIA COLOR BARS (NTSC)

Mode

(Swap Disabled)

Byte

565RGB

First

Second

555RGB

First

Second

444xRGB

First

Second

x444RGB

First

Second

1. PIXCLK is 54 MHz when EXTCLK is 27 MHz.

TABLE 30. EIA COLOR BARS (NTSC)

Mode

DOUT_LSB1

DOUT_LSB0

10-bit Output

1. PIXCLK is 27 MHz when EXTCLK is 27 MHz.

ASX340AT Datasheet(PDF) 37 Page - ON Semiconductor

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