ASX340AT datasheet(40/54 Pages) ONSEMI

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ASX340AT

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TABLE 31. PARALLEL DIGITAL OUTPUT I/O TIMING

(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;

VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; Default slew rate)

Signal

Parameter

Conditions

Min

Typ

Max

Unit

EXTCLK

fextclk

MHz

textclk_period

18.52

166.67

EXTCLK

Duty cycle

PIXCLK1

fpixclk

MHz

tpixclk_period

18.52

37.04

166.67

Duty cycle

DATA[7:0]

tpixclkf_dout

1.55

–

1.9

tdout_su

–

tdout_ho

–

FV/LV

tpixclkf_fvlv

1.6

–

3.05

tfvlv_su

–

tfvlv_ho

–

TABLE 32. SLEW RATE FOR POXCLK AND DOUT

(fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;

VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; T = 25°C; CLOAD = 40 pF)

PIXCLK

DOUT[7:0]

Unit

R0x1E [10:8]

Rise Time

Fall Time

R0x1E [2:0]

Rise Time

Fall Time

000

15.0

13.5

001

9.0

8.5

010

7.0

6.9

010

6.8

6.0

011

5.2

5.0

011

5.2

4.8

100

4.0

3.8

100

3.8

3.5

101

3.0

2.8

101

3.3

110

2.4

2.2

110

3.0

111

1.9

1.7

111

2.8

Figure 42. Slew Rate Timing

90%

10%

trise

t fall

PIXCLK

D OUT

t rise

tfall

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