ASX340AT datasheet(41/54 Pages) ONSEMI

Part #	ASX340AT

Description	1/4?릋nch Color CMOS NTSC/PAL Digital Image SOC

PDF	54 Pages

Scroll/Zoom	100%

Manufacturer	ONSEMI [ON Semiconductor]

Direct Link	http://www.onsemi.com

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ASX340AT

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Configuration Timing

During start-up, the Dout_LSB0, LV and FV are sampled.

Setup and hold timing for the RESET_BAR signal with

respect to DOUT_LSB0, LV, and FV are shown in Figure 38

and Table 30. These signals are sampled once by the on-chip

firmware, which yields a long tHOLD time.

Figure 43. Configuration Timing

tSETUP tHOLD

Valid Data

RESET_BAR

LINE_VALID

TABLE 33. CONFIGURATION TIMING

Signal

Parameter

Min

Typ

Max

Units

DOUT_LSB0, FRAME_VALID,

LINE_VALID

tSETUP

μs

tHOLD

μs

1. Table data is based on EXTCLK = 27 MHz.

Figure 44. Power Up Sequence

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL

VDD_DAC (2.8)

EXTCLK

RESET_BAR

VDD_IO (2.8)

Hard Reset

Internal

Initialization

Patch Config

SPI or Host

Streaming

TABLE 34. POWER UP SEQUENCE

Definition

Symbol

Min

Typical

Max

Unit

VDD_PLL to VAA/VAA_PIX

–

VAA/VAA_PIX to VDD_IO

–

ASX340AT Datasheet(PDF) 41 Page - ON Semiconductor

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