AS4C2M32SA datasheet(12/54 Pages) ALSC

12 / 54 page

Figure 13. Write to Precharge

Don’t Care

CLK

ADDRESS

COMMAND

tRP

DQM

tWR

WRITE

Precharge

NOP

Activate

NOP

BANK

COL n

BANK(S)

ROW

DIN

N+1

NOP

Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.

Write and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A7 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after the

write operation. Once this command is given, any subsequent command can not occur within a time

delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in

this command and the auto precharge function is ignored.

Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)

CLK

DIN A0

DIN A1

COMMAND

Bank A

Activate

NOP

WRITE A

Auto Precharge

NOP

Bank A

Activate

tDAL=tWR+tRP

tDAL

Begin AutoPrecharge

Bank can be reactivated at

completion of tDAL

Mode Register Set command

(RAS# = "L", CAS# = "L", WE# = "L", A0-A10 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The Mode

Mode register to make SDRAM useful for a variety of different applications. The default values of the

Mode Register after power-up are undefined; therefore this command must be issued at the power-up

sequence. The state of pins A0~A10 and BA0, 1 in the same cycle is the data written to the mode

figure). The contents of the mode register can be changed using the same command and the clock

cycle requirements during operation as long as all banks are in the idle state.

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Confidential

-12/54-

Rev.1.0 Sep. 2015

AS4C2M32SA Datasheet(PDF) 12 Page - Alliance Semiconductor Corporation

AS4C2M32SA Datasheet(HTML) 12 Page - Alliance Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL