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TVP7002IPZP Datasheet(PDF) 20 Page - Texas Instruments |
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TVP7002IPZP Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 58 page  TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Embedded Syncs Standard embedded syncs insert SAV and EAV codes into the data stream on the rising and falling edges of AVID. These codes contain the V and F bits that also define vertical timing. Table 7 gives the format of the SAV and EAV codes. H = 1 always indicates EAV. H = 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. The P bits are protection bits: P3 = V xor H P2 = F xor H P1 = F xor V P0 = F xor V xor H Table 7. EAV and SAV Sequence Y9 (MSB) Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Preamble 1 1 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 0 0 Status 1 F V H P3 P2 P1 P0 0 0 The pixel locations where SAV/EAV embedded sync codes are inserted can be programmed using the AVID Start Pixel and AVID Stop Pixel I2C registers. The AVID start location is determined from the HSYNC interval, horizontal back porch interval (Hbp) and a digital process delay factor (PDELAY) required for compensation of internal TVP7002 delays. An additional four bytes must be added to the active pixel interval between AVID start and AVID stop to accommodate embedded sync insertion. AVID Start Pixel = PDELAY + HSYNC + Hbp AVID Stop Pixel = AVID Start Pixel + Active Pixels + 4 NOTE Some AVID Stop Pixel calculations will exceed the HPLL-Feedback Register setting, or total pixels per line. When this occurs, subtract total pixels per line from AVID Stop Pixel. NOTE PDELAY is typically 27 pixels but may vary slightly depending on other TVP7002 settings such as the Sync-on-Green Threshold setting (I2C register 10h) and the SOG LPF setting (I2C register 1Ah). The line numbers where the embedded V-bit and F-bit occur are controlled by I2C registers 44h to 49h, which define the vertical blanking interval and field start positions. See Table 8 for typical embedded syncs settings. Table 8. Typical Embedded Sync Settings VBLK VBLK VBLK VBLK F-bit F-bit Output AVID Start Pixel AVID Stop Pixel Field 0 Field 1 Field O Field 1 Field 0 Field 1 Input Format Format Start Line Start Line Duration Duration Start Line Start Line REG 15h REG 41h REG 40h REG 43h REG 42h REG 44h REG 45h REG 46h REG 47h REG 48h REG 49h 480i60Hz 47h 00h 95h 00h 0Fh 01h 01h 13h 13h 02h 01h 480p60Hz 47h 00h 93h 00h 0Dh 09h 09h 2Dh 2Dh 00h 00h 720p60Hz 47h 01h 47h 06h 4Bh 05h 05h 1Eh 1Eh 00h 00h 1080i60Hz 47h 01h 07h 08h 8Bh 02h 02h 16h 17h 00h 00h 1080p60Hz 47h 01h 07h 08h 8Bh 04h 04h 2Dh 2Dh 00h 00h 20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: TVP7002 |
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