CS8405A

16

DS469PP4

7.

CONTROL PORT REGISTER SUMMARY

7.1

MEMORY ADDRESS POINTER (MAP)

INCR - Auto Increment Address Control Bit

Default = ‘0’

0 - Disable

1- Enable

MAP6:MAP0 - Register Address

Note:

Reserved registers must not be written to during normal operation. Some reserved registers are used for

test modes, which can completely alter the normal operation of the CS8405A.

Addr

Function

7

6

5

4

3

2

1

0

0

Reserved

0

0

0

0

0

0

0

0

1

Control 1

0

VSET

0

MUTEAES

0

INT1

INT0

TCBLD

2

Control 2

0

0

0

0

0

MMT

MMCST

MMTLR

3

Data Flow Control

0

TXOFF

AESBP

0

0

0

0

0

4

Clock Source Control

0

RUN

CLK1

CLK0

0

0

0

0

5

Serial Input Format

SIMS

SISF

SIRES1

SIRES0

SIJUST SIDEL

SISPOL SILRPOL

6

Reserved

0

0

0

0

0

0

0

0

7

Interrupt 1 Status

TSLIP

0

0

0

0

0

EFTC

0

8

Interrupt 2 Status

0

0

0

0

0

EFTU

0

0

9

Interrupt 1 Mask

TSLIPM

0

0

0

0

0

EFTCM

0

A

Interrupt 1 Mode (MSB) TSLIP1

0

0

0

0

0

EFTC1

0

B

Interrupt 1 Mode (LSB)

TSLIP0

0

0

0

0

0

EFTC0

0

C

Interrupt 2 Mask

0

0

0

0

0

EFTU

M

00

D

Interrupt 2 Mode (MSB)

0

0

0

0

0

EFTU1

0

0

E

Interrupt 2 Mode (LSB)

0

0

0

0

0

EFTU0

0

0

F-11 Reserved

0

0

0

0

0

0

0

0

12

CS Data Buffer Control

0

0

BSEL

0

0

EFTCI

CAM

0

13

U Data Buffer Control

0

0

0

UD

UBM1

UBM0

0

EFTUI

1E-1D Reserved

0

0

0

0

0

0

0

0

1F-37 C or U Data Buffer

7F

ID and Version

ID3

ID2

ID1

ID0

VER3

VER2

VER1

VER0

Table 1. Control Register Map Summary

7

6

5

43210

INCR

MAP6

MAP5

MAP4

MAP3

MAP2

MAP1

MAP0