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ML610Q421 Datasheet(PDF) 9 Page - LAPIS Semiconductor Co., Ltd. |
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ML610Q421 Datasheet(HTML) 9 Page - LAPIS Semiconductor Co., Ltd. |
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9 / 37 page ![]() FEDL610Q421-03 ML610Q421/ML610Q422 ML610Q421 Chip Pin Layout & Dimension SEG49 89 58 SEG18 COM0 90 57 SEG17 COM1 91 56 SEG16 COM2 92 55 SEG15 COM3 93 54 SEG14 COM4 94 53 SEG13 COM5 95 52 SEG12 COM6 96 51 SEG11 COM7 97 50 SEG10 PA0 98 49 SEG9 PA1 99 48 SEG8 PA2 100 47 SEG7 PA3 101 46 SEG6 PA4 102 45 SEG5 PA5 103 44 SEG4 PA6 104 43 SEG3 PA7 105 42 SEG2 P20/LED0 106 P21/LED1 107 P22/LED2 108 P40/SDA 109 P41/SCL 110 Vss 111 AVSS 112 VREF 113 AIN0 114 AIN1 115 AVDD 116 41 40 39 38 37 36 35 34 33 32 30 31 SEG1 SEG0 VDD P11 P10 Vss P03 P02 P01 P00 C3 C4 2.98mm 3.02mm Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.98 mm × 3.02 mm PAD count: 116 pins Minimum PAD pitch: 80 µm PAD aperture: 70 µm × 70 µm Chip thickness: 350 µm Voltage of the rear side of chip: VSS level Figure 5 ML610Q421 Chip Layout & Dimension 9/37 |
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