ML7344CE datasheet(85/154 Pages) LAPIS

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FEDL7344C/E/J-05

ML7344C/E/J

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(2) Interrupt generation timing

In each interrupt generation, timing from reference point to interrupt generation (notification) are described in

the following table. Timeout procedure for interrupt notification waiting are also described below.

NOTE:

(1)The values are described in units of “bit cycle” in the below table is the value at 100kbps. If using other data

rate, please esitimate with appropriate “bit cycle”.

(2)Below table uses the following format for TX/RX data.

(3)Even if each interrupt notification is masked, in case of interrupt occurence, interrupt elements are stored

internally. Therefore, as soon as interrupt notification is unmasked, interrupt will generate.

Interrupt notice

Reference point

Timing from reference point to interrupt generation

or interrupt generation timing

RESETN release

(upon power-up)

50μs

INT[0]

CLK stabilization

completion

SLEEP release

(recovered from SLEEP)

50μs

INT[1]

VCO calibration

completion

VCO calibration start

230μs

PLL unlock

detection

(TX) during TX after PA enable.

(RX) during RX after RX enable.

INT[2]

VCO CAL request

(TX) rising edge of PA_ON signal.

(RX) rising edge of RX enable signal.

TX_ON command

(IDLE) 1406μs

(RX) 1188μs

RX_ON command

(IDLE) μs

(TX) 244μs

TRX_OFF command

(TX) 147μs

(RX) 4μs

INT[3]

RF state

transition

completion

Force_TRX_OFF

Command

(TX) 147μs

(RX) 4μs

(TX)

TX_ON command

(*1)

NRZ coding, Empty trigger level is set to 0x02

RF wake-up(1406μs)+ 35 byte (preamble to 22

nd Data byte) *

8bit *10(bit cycle) =4206μs

INT[4]

FIFO-Empty

detection

(RX) -

By FIFO read, remaining FIFO data is under trigger level

(TX) -

By FIFO write, FIFO usage exceed trigger level

INT[5]

FIFO-FULL

detection

(RX)

SyncWord detection

NRZ coding, Full trigger level is set to 0x05

6byte (Length to 5

th Data byte) * 8bit * 10μs(bit cycle) = 480μs

INT[6]

Wake-up timer

completion

SLEEP setting

Wake-up timer is completed.

For details, please refer to “wake-up timer”

INT[7]

Clock calibration

completion

Calibration start

Calibration timer is completed.

For details, please refer to “low speed clock shift detection

function”.

(*1) Before issuing TX_ON, writing full-length TX data to the TX_FIFO.

2 byte

10 byte

1 byte

24 byte

2 byte

Preamble

SyncWord

Length

User data

CRC

ML7344CE Datasheet(PDF) 85 Page - LAPIS Semiconductor Co., Ltd.

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