ML7344CE datasheet(30/154 Pages) LAPIS

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FEDL7344C/E/J-05

ML7344C/E/J

30/154

●Notes to set RF state

ML7344 is able to change the internal RF state transition autonomously (without commands from MCU) as

well as RF state change commands from MCU. (please refer to ”LSI state transition instruction”). If both

timing of operation (autonomous state and state change from MCU command) overlapped, unintentional RF

state may occur. Timing of autonomous state RF change is described in the following table.

Care must be taken not to overlap the conditions.

Function

RF state change

(before → after)

RF state transition timing (not from

Host MCU command)

Recommended process

Automatic TX

After TX data transfer completion interrupt

occurs, {value [TX_RATE_H/L: B1 0x02/03)] ×

2 / 26}[μs] period

FAST_TX

mode

TRX_OFF/RX_ON

→TX_ON

When FIFO write access exceed trigger level

+1, {value [RX_RATE1_H/L:B1 0x04/05] × 5 /

26}[μs] period.

TX_ON→TRX_OFF

TX_ON→RX_ON

RF state setting

after

TX completion

TX_ON→SLEEP

After TX completion interrupt (INT[16] group3),

{value [TX_RATE_H/L:B1 0x02/03] × 2 / 26}

[μs] period

RX_ON→TRX_OFF

RX_ON→TX_ON

RF state setting

after

RX completion

RX_ON→SLEEP

After RX completion interrupt (INT[8] group2),

{value [RX_RATE1_H/L:B1 0x04/05] × 2 /

26}[μs] period

SLEEP→TX_ON

SLEEP→RX_ON

After wake-up timer completion interrupt

(INT[6] group1), 1 clock cycle period defined by

WUT_CLK_SET[3:0] ([WUT_CLK_SET: B0

0x2E(3-0)]).

Write access to [RF_STATUS:B0

0x0B] is possible after RF state

transition

completion

interrupt

(INT[3] group1), or move to the

state

defined

GET_TRX

([RF_STATUS:B0 0x0B(7-4)]).

SLEEP→VCO_CAL

→TX_ON

Wake-up timer

SLEEP→VCO_CAL

→RX_ON

After wake-up timer completion interrupt

(INT[6] group1), before VCO calibration

completion interrupt (INT[1] group1).

Write access to [RF_STATUS:B0

0x0B] and BANK2 is possible

after VCO calibration completion

interrupt (INT[1] group1).

TX_ON→SLEEP

Continuous

operation timer

RX_ON→SLEEP

After continuous operation timer completion, 1

clock cycle period defined by WUT_CLK_SET

[3:0] ([WUT_CLK_SET: B0 0x2E(3-0)]).

High speed

carrier checking

RX_ON→SLEEP

After CCA completion interrupt (INT[18]

group3), duration 6.3[μs].

Write access to [RF_STATUS:B0

0x0B] is possible after RF state

transition completion interrupt

(INT[3] group1), or move to the

state defined by GET_TRX

([RF_STATUS:B0 0x0B(7-4)]).

PLL unlock

detection

TX_ON→TRX_OFF

After PLL unlock detection interrupt (INT[2]

group1) occurs, duration 147[μs].

Write access to [RF_STATUS:B0

0x0B] is possible 147μs after PLL

unlock interrupt (INT[2] group1)

detected.

ML7344CE Datasheet(PDF) 30 Page - LAPIS Semiconductor Co., Ltd.

ML7344CE Datasheet(HTML) 30 Page - LAPIS Semiconductor Co., Ltd.

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