XRT8001IP datasheet(18/48 Pages) EXAR

18 / 48 page

XRT8001

Rev. 1.01

D0 – PL1EN (PLL # 1 Enable Select)

This bit-field permits the user to enable or disable PLL

# 1, within the XRT8001 WAN Clock. Setting this bit-

field to “1” enables PLL # 1 for Frequency Synthesis.

Conversely, setting this bit-field to “0” disables PLL #

1 for Frequency Synthesis.

3.2.2 Command Register CR1 (Address = 0x01)

D4 – D1: (M4 – M1)

These bit-fields are used to support configuration

implementation for both the “Forward/Master” and “E1

to T1 - Forward/Master” Modes. In both the “Forward/

Master” and “E1 to T1 - Forward/Master” Modes, the

XRT8001 WAN Clock will be receiving either a “N x

1.544MHz” or a “N x 2.048MHz” clock signal. The M4

through M1 bit-fields, within this register, permit the

user to specify the value of “N”. As a consequence, the

XRT8001 can be configured to accept a maximum

frequency of “16 x 1.544MHz” or “16 x 2.048MHz”.

D0 – PL2EN (PLL # 2 Enable Select)

This bit-field permits the user to enable or disable PLL

# 2, within the XRT8001 WAN Clock. Setting this bit-

field to “1” enables PLL # 2 for Frequency Synthesis.

Conversely, setting this bit-field to “0” disables PLL #

2 for Frequency Synthesis.

3.2.3 Command Register CR2 (Address = 0x02)

D4 – D0 (SEL1[4:0])

These bit-fields are used to support configuration

implementation for both the “Forward/Master”, “Frac-

tional T1/E1 Reverse/Master” and “High Speed – Re-

verse” Modes.

In the Forward/Master Mode

In the “Forward/Master” Mode, the XRT8001 WAN

Clock will output either a “K x 56kHz” or a “K x 64kHz”

clock signal via the CLK1 output pin. These five (5) bit-

fields within Command Register CR2 are used to define

the value of “K” for the CLK1 Output. As a conse-

quence, the XRT8001 can be configured to generate a

maximum frequency of “32 x 56kHz” or “32 x 64kHz” via

the CLK1 output pin.

In the “Fractional T1/E1 Reverse/Master” Mode

In the “Fractional T1/E1 Reverse/Master” Mode, the

XRT8001 WAN Clock will be receiving either a “P x

56kHz” or a “P x 64kHz” clock signal via the “FIN” input

pin. The XRT8001 WAN Clock will, in response, gen-

erate either a 1.544MHz or a 2.048MHz clock signal via

the CLK1 and/or CLK2 output pins. These five (5) bit-

fields are used to define the value of “P”.

As a

consequence, the XRT8001 can be configured to

accept a maximum frequency of “32 x 56kHz” or “32 x

64kHz”.

XRT8001IP Datasheet(PDF) 18 Page - Exar Corporation

XRT8001IP Datasheet(HTML) 18 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL