XRT8001IP datasheet(44/48 Pages) EXAR

44 / 48 page

XRT8001

Rev. 1.01

10.1 Reading Figures 25 and 26

Figures 25 and 26 are linear (as opposed to logarithmic)

plots. The Jitter Gain is computed via the following

equation.

Jitter

Gain

(at

Jitter

Frequency

(Jitter_Amplitude_CLK)/(Jitter_Amplitude_FIN)

Where:

• Jitter_Amplitude_FIN = The Jitter Amplitude ap-

plied to the “FIN” input (at Jitter Frequency f).

• Jitter_Amplitude_CLK = The Jitter Amplitude

measured at the “CLK1” or “CLK2” output, when

“Jitter_Amplitude_FIN” is applied to the FIN input

in of the XRT8001.

Hence, the Jitter Gain is not expressed in terms of dB,

but simply a ratio of two numbers.

Wherever the Jitter Gain exceeds “1.0” in value, then,

for those “Jitter Frequencies” the XRT8001 amplifies

Jitter (e.g., the amplitude of the jitter, as it propagates

from the “FIN” input to the “CLK1” or CLK2” output,

increases).

Conversely, wherever the Jitter Gain falls below “1.0”

in value, then for those “Jitter Frequencies” the

XRT8001 attenuates jitter (e.g., the amplitude of the

jitter, as it propagates from the “FIN” input to the “CLK1”

or “CLK2” output, decreases).

Figures 25 and 26 indicate that for Jitter Frequencies,

ranging between 100Hz and 1100Hz, the XRT8001

amplifies Jitter. Further, these figures also indicate

that for Jitter Frequencies greater than 1100Hz, that

the XRT8001 attenuates Jitter.

10.2 Test Conditions for Measurements associated

with Figures 25 and 26

• Power Supply voltage either 3.3V or 5.V

• Input Clock Frequency = 2.048MHz

• Output Clock Frequency = 2.048MHz

• Input Jitter Amplitude = 0.25Upp.

• Ambient Temperature = 25°C.

11.0 PCB layout guidelines for the XRT8001

• Use a multi-layer circuit board with separate plane

layers for “+5V” (or 3.3V) and “Ground” .

• BypasstheAnalogVDDpintogroundwitha6.9mF

“ceramic” capacitor.

• Use large “vias” located close to the IC package to

ensure that Digital VDD (e.g., pins 7, 12 and 15)

and Digital Ground (e.g., pins 4, 5 and 14) have a

low inductance path to the +5V (+3.3V) and Ground

Planes, respectively.

• BypasstheDigitalVDDpins(pin10)togroundwith

a 0.1mF ceramic capacitors that are located as

close as possible to the IC package.

12.0 Comparing the XRT8001 with the earlier pin-

compatible XRT8000

The XRT8001 is pin-to-pin compatible with the

XRT8000. However, there are some functional differ-

ences between these two products. These differences

are summarized below.

1) The XRT8001 can be configured to generate frequen-

cies up to 2.048MHz, 4.096MHz, 8.192MHz or

16.384MHz.

The Maximum Frequency that the XRT8000 can gen-

erate is either 2.048MHz or 1.544MHz

2) The XRT8001 can be configured to accept an E1 rate

clock signal and synthesize a T1 rate clock signal. The

XRT8001 can also synthesize an E1 rate clock signal,

when provided with a T1 rate clock signal

The XRT8000 can be configured to accept a T1 rate

clock signal (e.g., 1.544MHz) and can be easily config-

ured to synthesize an E1 rate clock signal (e.g.,

2.048MHz).

However, the XRT8000 cannot be configured to accept

an E1 rate clock signal and synthesize a T1 rate clock

signal.

XRT8001IP Datasheet(PDF) 44 Page - Exar Corporation

XRT8001IP Datasheet(HTML) 44 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL