XRT8001IP datasheet(36/48 Pages) EXAR

36 / 48 page

XRT8001

Rev. 1.01

7.1 Synthesizing an “M x 2.048MHz” clock signal,

such that “M” can take on the value of “1”, “2”, “4”,

or “8” with a clock signal of 2.048MHz

Figure 21 presents a possible approach that can be

used. In this example, the user takes the 2.048MHz

clock signal, and runs it through an external “Divide-

by-32” counter (which is realized with two

74AHCT193). This “Divide-by-32” counter generates

a 64kHz clock signal, which is applied to the “FIN”

input pin of the XRT8001.

Serial_Data_Out

64kHz Clock Signal

Clear_Counter

2.048MHz_CLOCK

XRT8001

FIN

SCLK

SDO

SDI

MSB

CLK1

CLK2

LOCKDET

XRT8000_Select

M x 2.048MHz_CLOCK

WAN_CLOCK_PLL_LOCK_STATUS

74AHCT193

LOAD

CLR

Serial_Clock

74AHCT193

LOAD

CLR

M x 2.048MHz_CLOCK

+5V

Serial_Data_In

Figure 21: Circuit that inputs a 2.048MHz clock and generates a “M” x 2.048MHz clock

If the user configures the XRT8001 WAN Clock to

operate in the “

High Speed – Reverse” Mode, then

it will accepts a 64kHz clock signal (via the FIN

input) and generates an “M x 2.048MHz” clock

signal via both the CLK1 and CLK2 outputs.

NOTES:

In this configuration, “M” can be configured to be of

value “1”, “2”, “4” or “8”.

The steps required to configure the XRT8001 into the

“High Speed – Reverse” Mode are presented below.

7.2 Configuring the XRT8001 WAN Clock to operate

in the “High Speed – Reverse” Mode.

The following is a “six-step” procedure to configure the

XRT8001 WAN Clock into the “High Speed – Reverse”

Mode.

STEP 1 – Configure the XRT8001 to operate in the

“SLAVE” Mode, by pulling the “MSB” input pin (pin 8)

to GND (low).

STEP 2 – Write the binary expression “1101” into bit-

fields D4 through D1, within Command Register, CR0,

as indicated below.

Command Register, CR1 (Address = 0x01)

PL2EN

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