LT1763CS8 datasheet(12/16 Pages) LINER

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LT1763 Series

1763fa

APPLICATIONS INFORMATION

plus the ADJ pin bias current. The ADJ pin bias current,

30nA at 25

°C, flows through R2 into the ADJ pin. The

output voltage can be calculated using the formula in

Figure 2. The value of R1 should be no greater than 250k

to minimize errors in the output voltage caused by the ADJ

pin bias current. Note that in shutdown the output is turned

off and the divider current will be zero. Curves of ADJ Pin

Voltage vs Temperature and ADJ Pin Bias Current vs

Temperature appear in the Typical Performance Charac-

teristics section.

Figure 3. Stability

OUTPUT CAPACITANCE (

µF)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

310

1763 F03

6 78 9

STABLE REGION

CBYP = 330pF

CBYP ≥ 1000pF

CBYP = 100pF

CBYP = 0

µs, with total output voltage deviation of less than 2.5%

(see LT1763-5 Transient Response in the Typical Perfor-

mance Characteristics). However, regulator start-up time

is inversely proportional to the size of the bypass capaci-

tor, slowing to 15ms with a 0.01

µF bypass capacitor and

µF output capacitor.

Output Capacitance and Transient Response

The LT1763 regulators are designed to be stable with a

wide range of output capacitors. The ESR of the output

capacitor affects stability, most notably with small capaci-

tors. A minimum output capacitor of 3.3

µF with an ESR of

Ω or less is recommended to prevent oscillations. The

LT1763-X is a micropower device and output transient

response will be a function of output capacitance. Larger

values of output capacitance decrease the peak deviations

and provide improved transient response for larger load

current changes. Bypass capacitors, used to decouple

individual components powered by the LT1763-X, will

increase the effective output capacitor value. With larger

capacitors used to bypass the reference (for low noise

operation), larger values of output capacitors are needed.

For 100pF of bypass capacitance, 4.7

µF of output capaci-

tor is recommended. With a 1000pF bypass capacitor or

larger, a 6.8

µF output capacitor is recommended.

The shaded region of Figure 3 defines the range over which

the LT1763 regulators are stable. The minimum ESR

needed is defined by the amount of bypass capacitance

used, while the maximum ESR is 3

Ω.

1763 F02

OUT

VIN

VOUT

ADJ

GND

LT1763

InA

OUT

ADJ









()( )

=°

122

AT 25 C

OUTPUT RANGE = 1.22V TO 20V

Figure 2. Adjustable Operation

The adjustable device is tested and specified with the ADJ

pin tied to the OUT pin for an output voltage of 1.22V.

Specifications for output voltages greater than 1.22V will

be proportional to the ratio of the desired output voltage to

1.22V: VOUT/1.22V. For example, load regulation for an

output current change of 1mA to 500mA is – 2mV typical

at VOUT = 1.22V. At VOUT = 12V, load regulation is:

(12V/1.22V)(–2mV) = – 19.6mV

Bypass Capacitance and Low Noise Performance

The LT1763 regulators may be used with the addition of a

bypass capacitor from VOUT to the BYP pin to lower output

voltage noise. A good quality low leakage capacitor is

recommended. This capacitor will bypass the reference of

the regulator, providing a low frequency noise pole. The

noise pole provided by this bypass capacitor will lower the

output voltage noise to as low as 20

µVRMS with the

addition of a 0.01

µF bypass capacitor. Using a bypass

capacitor has the added benefit of improving transient

response. With no bypass capacitor and a 10

µF output

capacitor, a 10mA to 500mA load step will settle to within

1% of its final value in less than 100

µs. With the addition

of a 0.01

µF bypass capacitor, the output will settle to

within 1% for a 10mA to 500mA load step in less than

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