©2015 Silicon Storage Technology, Inc.

DS20005036C

04/15

9

64 Mbit SPI Serial Dual I/O Flash

SST25VF064C

EOL Data Sheet

Busy

The Busy bit determines whether there is an internal Erase or Program operation in progress. A ‘1’ for

the Busy bit indicates the device is busy with an operation in progress. A ‘0’ indicates the device is

ready for the next valid operation.

Write Enable Latch (WEL)

The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the

Write-Enable-Latch bit is set to ‘1’, it indicates the device is Write enabled. If the bit is set to ‘0’ (reset),

it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)

commands. The Write-Enable-Latch bit is automatically reset under the following conditions:

•

Power-up

•

Write-Disable (WRDI) instruction completion

•

Write-Status Register instruction completion

•

Page-Program instruction completion

•

Dual-Input Page-Program instruction completion

•

Sector-Erase instruction completion

•

Block-Erase instruction completion

•

Chip-Erase instruction completion

•

Program SID instruction completion

•

Lockout SID instruction completion

Block Protection (BP3,BP2, BP1, BP0)

The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area, as shown in Table

5, to be software protected against any memory Write (Program or Erase) operation. The Write-Status-

Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is

high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits

are all 0. After power-up, BP3, BP2, BP1 and BP0 are set to the defaults specified in Table 5.

Block Protection Lock-Down (BPL)

vents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high