MIC4102 datasheet(13/28 Pages) MICROCHIP

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DS20005575A-page 13

MIC4102

5.0

FUNCTIONAL DESCRIPTION

The MIC4102 is a high voltage, non-inverting,

synchronous MOSFET driver that uses a single PWM

input signal to alternately drive both high-side and

low-side N-Channel MOSFETs. The Functional Block

Diagram of the MIC4102 is shown on page two.

The MIC4102 input is TTL-compatible. The high-side

output buffer includes a high speed level-shifting circuit

that is referenced to the HS pin. An internal diode is

used as part of a bootstrap circuit to provide the drive

voltage for the high-side output.

5.1

Startup and UVLO

The UVLO circuit forces both driver outputs low until

the supply voltage exceeds the UVLO threshold. The

low-side UVLO circuit monitors the voltage between

the VDD and VSS pins. The high-side UVLO circuit

monitors the voltage between the HB and HS pins.

Hysteresis in the UVLO circuit prevents noise and finite

circuit impedance from causing chatter during turn-on.

The VDD pin voltage is supplied to the HS pin through

the internal bootstrap diode. The HB pin voltage will

always be a diode drop less than VDD.

5.2

Input Stage

The MIC4102 utilizes a TTL-compatible input stage.

The PWM input pin is referenced to the VSS pin. The

voltage state of the input signal does not change the

quiescent current draw of the driver. The threshold

level is independent of the VDD supply voltage and

there is no dependence between IVDD and the input

signal amplitude. This feature makes the MIC4102 an

excellent level translator that will drive high threshold

MOSFETs from a low voltage PWM IC.

5.3

Low-Side Driver

A block diagram of the low-side driver is shown in

Figure 5-1. The low-side driver is designed to drive a

ground (VSS pin) referenced N-channel MOSFET. Low

driver impedances allow the external MOSFET to be

turned on and off quickly. The rail-to-rail drive capability

of the output ensures a low RDS(ON) from the external

MOSFET.

A low level applied to PWM pin will cause the HO

output to go low and the LO output to go high. The

upper driver FET turns on and VDD is applied to the

gate of the external MOSFET. A high level on the PWM

pin forces the LO output low by turning off the upper

driver and turning on the lower driver which ground the

gate of the external MOSFET.

Pulling the LS pin low disables the LO pin.

FIGURE 5-1:

Low-Side Driver Block

Diagram.

5.4

High-Side Driver and Bootstrap

Circuit

A block diagram of the high-side driver and bootstrap

circuit is shown in Figure 5-2. This driver is designed to

drive a floating N-channel MOSFET, whose source

terminal is referenced to the HS pin.

FIGURE 5-2:

High-Side Driver Block

Diagram.

A low-power, high-speed, level-shifting circuit isolates

the low-side (VSS pin) referenced circuitry from the

high-side (HS pin) referenced driver. Power to the

high-side driver and UVLO circuit is supplied by the

bootstrap circuit while the voltage level of the HS pin is

shifted high.

The bootstrap circuit consists of an internal diode and

external capacitor, CB. In a typical application, such as

the synchronous buck converter shown in Figure 5-3,

the HS pin is at ground potential while the low-side

MOSFET is on. The internal diode allows capacitor CB

to charge up to VDD – VD during this time (where VD is

the forward voltage drop of the internal diode). After the

low-side MOSFET is turned off and the HO pin turns

on, the voltage across capacitor CB is applied to the

EXTERNAL

FET

DRIVE

SIGNAL

EXTERNAL

FET

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