DAC8541

SLAS353 − DECEMBER 2001

5

www.ti.com

MIN

TYP

MAX

UNIT

tw1

Pulse width: CS low for valid write

20

ns

tsu1

Setup time: R/W low before CS falling (see Note 4)

0

ns

tsu2

Setup time: data in valid before CS falling

0

ns

th1

Hold time: R/W low after CS rising (see Note 4)

10

ns

th2

Hold time: data in valid after CS rising

15

ns

tw2

Pulse width: CS low for valid read

40

ns

tsu3

Setup time: R/W high before CS falling

30

ns

td1

Delay time: data out valid after CS falling

60

80

ns

th3

Hold time: R/W high after CS rising

10

ns

th4

Hold time: data out valid after CS rising

5

20

ns

tsu4

Setup time: LDAC rising after CS falling (see Note 4)

10

ns

td2

Delay time: CS low after LDAC rising

50

ns

tw3

Pulse width: LDAC low

40

ns

tw4

Pulse width: LDAC high

40

ns

tw5

Pulse width: CS high (see Note 4)

80

ns

tsu5

Setup time: RSTSEL valid before RST rising

0

ns

th5

Hold time: RSTSEL valid after RST rising

20

ns

tw6

Pulse width: RST low

40

ns

tw7

Pulse width: RST high

40

ns

tS

VOUT Settling time (settling time for a full scale code change)

10

µs

NOTE 4: Simplified operation: CS and W/R can be tied low if the DAC8541 is the only device on the bus and Read operation is not needed. In

this case, LDAC is still required to update the output of the DAC and tsu(4) is from Data In Valid to LDAC Rising.

tw1

tw5

tw2

tsu1

th1

tsu3

th3

th4

tsu2

th2

td1

tsu4

td2

tw4

tw3

ts

±0.003% of FSR Error Bands

Data Out Valid

Data In Valid

CS

R/W

Data I/O

DB0−DB15

LDAC

VOUT

Figure 1. Data Read/Write Timing