DAC8541

SLAS353 − DECEMBER 2001

14

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THEORY OF OPERATION

resistor string

The resistor string section is shown in Figure 30. It is simply a string of resistors, each of which has a value of

R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This

voltage is then presented to the output amplifier by closing one of the switches connecting the string to the

voltage reference inputs section.)

output amplifier

The output buffer amplifier is capable of generating near rail-to-rail voltages on its output, which gives an output

of 2 k

Ω in parallel with 1000 pF to AGND while remaining stable. The source and sink capabilities of the output

amplifier can be seen in the typical curves. The slew rate of the DAC8541 is typically 1 V/

µs with a typical

full-scale settling time of 8

µs.

Other signal conditioning circuitry may also be connected between these points for specific applications.

parallel interface

The DAC8541 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input

register. (See the timing characteristics section for detailed information for a typical write or read command.)

In addition to the data, CS, and R/W inputs, the DAC8541’s interface also provides powerdown, LDAC, data

format, and reset/reset-select control. Tables 1 and 2 show the control signal actions and data format,

respectively. These features are discussed in more detail in the remaining sections.

Table 1. DAC8541 CONTROL SIGNAL SUMMARY

CS

R/W

BTC/USB

LDAC

RST

RSTSEL

PD1

PD0

ACTION

H

X

X

X

X

X

X

X

Device data I/O is disabled on the bus.†

↓

L

X

X

H,L

X

L

L

Write initiated, present input data to the bus.

↓

H

X

X

H,L

X

L

L

Read initiated, data from input register is presented to data bus.

↑

X

X

X

H,L

X

L

L

Input data is latched when writing to the device.

X

X

X

↑

H,L

X

L

L

Data from input register is transferred to DAC register and VOUT is

updated.

X

X

L

X

X

X

X

X

Input/output data format is unipolar straight binary.

X

X

H

X

X

X

X

X

Input/output data format is binary 2s complement.

X

X

X

X

↑

L

L

L

DAC register and VOUT reset to min-scale. (If DAC is powered down

during reset, DAC register resets and VOUT will settle to min-scale

upon power up.)

X

X

X

X

↑

H

L

L

DAC register and VOUT reset to mid-scale. (If DAC is powered down

during reset, DAC register resets and VOUT will settle to mid-scale

upon power up.)

X

X

X

X

X

X

L

H

Powerdown device, VOUT impedance equals 1 kΩ to AGND

X

X

X

X

X

X

H

L

Powerdown device, VOUT impedance equals 100 kΩ to AGND

X

X

X

X

X

X

H

H

Powerdown device, VOUT impedance equals high impedance

† Only disables 16-bit data I/O interface. Other control lines remain active.