DAC8541YSLASH2K datasheet(16/21 Pages) TI

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DAC8541

SLAS353 − DECEMBER 2001

www.ti.com

THEORY OF OPERATION

power-down modes

The DAC8541 utilizes four modes of operation. These modes are programmable via two inputs (PD1 and PD0)

to the device. Table 3 shows how the state of these pins correspond to the mode of operation of the DAC8541.

Table 3. Modes of Operation for the DAC8541

PD1

PD0

OPERATING MODE

Normal operation

POWER-DOWN MODES

1 k

Ω to AGND

100 k

Ω to AGND

High impedance

When both pins are set to 0, the device works normally with its typical power consumption of 250

µA at

AVDD = 5 V. However, for the three power-down modes, the supply current falls to 200 nA at AVDD = 5 V (50 nA

at AVDD = 3 V). Not only does the supply current fall, but the VOUT terminal is internally switched from the output

of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the

device is known while in power-down mode. There are three different options: The output is connected internally

to AGND through a 1-k

Ω resistor, it is connected to AGND through a 100-kΩ resistor, or it is left open-circuited

(high impedance). The output stage is illustrated in Figure 31.

DAC

Powerdown

Circuitry

Amplifier

Resistor

Network

VOUT

VOUTSense

Figure 31. Output Stage During Power Down (High-Impedance)

All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC

when power-up resumes. The delay time required to exit power-down is typically 2.5

µs for AVDD = 5 V and 5

µs for AVDD = 3 V. (See the typical curves section for additional information.)

voltage reference inputs

Two voltage inputs provide the reference set points for the DAC architecture. These are VREFH and VREFL. For

typical rail-to-rail operation, VREFH should be equivalent to AVDD and VREFL tied to AGND. The output voltage

is given by:

OUT +

REF

* 2

REF

The use of the VREFL input allows minor adjustments to be made to the offset of the DAC output by applying

a small voltage to the VREFL input. The acceptable range is between −100 mV and 100 mV with respect to

AGND. A low output impedance source is needed, so that the accuracy of the DAC over its operating range is

not affected.

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