HY29F080 datasheet(16/38 Pages) HYNIX

16 / 38 page

Rev. 6.1/May 01

HY29F080

DQ[7] - Data# Polling

The Data# (“Data Bar”) Polling bit, DQ[7], indicates

to the host system whether an Automatic Algo-

rithm is in progress or completed, or whether the

device is in Erase Suspend mode. Data# Polling

is valid after the rising edge of the final WE# pulse

in the Program or Erase command sequence.

The system must do a read at the program ad-

dress to obtain valid programming status informa-

tion on this bit. While a programming operation is

in progress, the device outputs the complement

of the value programmed to DQ[7]. When the pro-

gramming operation is complete, the device out-

puts the value programmed to DQ[7]. If a pro-

gram operation is attempted within a protected

sector, Data# Polling on DQ[7] is active for ap-

proximately 2 µs, then the device returns to read-

ing array data.

The host must read at an address within any non-

protected sector scheduled for erasure to obtain

valid erase status information on DQ[7]. During

an erase operation, Data# Polling produces a “0”

on DQ[7]. When the erase operation is complete,

or if the device enters the Erase Suspend mode,

Data# Polling produces a “1” on DQ[7]. If all sec-

tors selected for erasing are protected, Data#

Polling on DQ[7] is active for approximately 100

µs, then the device returns to reading array data.

If at least one selected sector is not protected, the

erase operation erases the unprotected sectors,

and ignores the command for the selected sec-

tors that are protected.

When the system detects that DQ[7] has changed

from the complement to true data (or “0” to “1” for

erase), it should do an additional read cycle to read

valid data from DQ[7:0]. This is because DQ[7]

may change asynchronously with respect to the

other data bits while Output Enable (OE#) is as-

serted low.

Figure 7 illustrates the Data# Polling test algorithm.

DQ[6] - Toggle Bit I

Toggle Bit I on DQ[6] indicates whether an Auto-

matic Program or Erase algorithm is in progress

or complete, or whether the device has entered

the Erase Suspend mode. Toggle Bit I may be

read at any address, and is valid after the rising

edge of the final WE# pulse in the program or erase

command sequence, including during the sector

erase time-out. The system may use either OE#

or CE# to control the read cycles.

Successive read cycles at any address during an

Automatic Program algorithm operation (including

programming while in Erase Suspend mode)

cause DQ[6] to toggle. DQ[6] stops toggling when

the operation is complete. If a program address

falls within a protected sector, DQ[6] toggles for

approximately 2 µs after the program command

sequence is written, then returns to reading array

data.

While the Automatic Erase algorithm is operating,

successive read cycles at any address cause

DQ[6] to toggle. DQ[6] stops toggling when the

erase operation is complete or when the device is

placed in the Erase Suspend mode. The host may

use DQ[2] to determine which sectors are erasing

START

Read DQ[7:0]

at Valid Address (Note 1)

DQ[7] = Data?

YES

PROGRAM/ERASE

COMPLETE

DQ[5] = 1?

YES

Test for DQ[7] = 1?

for Erase Operation

Read DQ[7:0]

at Valid Address (Note 1)

DQ[7] = Data?

(Note 2)

YES

Test for DQ[7] = 1?

for Erase Operation

PROGRAM/ERASE

EXCEEDED TIME ERROR

Notes:

1. During programming, the program address.

During sector erase, an address within any non-protected sector

scheduled for erasure.

During chip erase, an address within any non-protected sector.

2. Recheck DQ[7] since it may change asynchronously at the same time

as DQ[5].

Figure 7. Data# Polling Test Algorithm

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