HY29F080 datasheet(7/38 Pages) HYNIX

7 / 38 page

Rev. 6.1/May 01

HY29F080

latched on the falling edge of WE# or CE#, which-

ever happens later. All data is latched on the ris-

ing edge of WE# or CE#, whichever happens first.

The ‘Device Commands’ section of this document

provides details on the specific device commands

implemented in the HY29F080.

Output Disable Operation

When the OE# input is at V

IH, output data from the

device is disabled and the data bus pins are placed

in the high impedance state.

Standby Operation

When the system is not reading from or writing to

the HY29F080, it can place the device in the

Standby mode. In this mode, current consump-

tion is greatly reduced, and the data bus outputs

are placed in the high impedance state, indepen-

dent of the OE# input. The Standby mode can

invoked using two methods.

The device enters the CE# CMOS Standby mode

if the CE# and RESET# pins are both held at V

± 0.5V. Note that this is a more restricted voltage

range than V

IH. If both CE# and RESET# are held

High, but not within V

CC ± 0.5V, the device will be

in the CE# TTL Standby mode, but the standby

current will be greater.

The device enters the RESET# CMOS Standby

mode when the RESET# pin is held at V

SS ± 0.5V.

If RESET# is held Low but not within V

SS ± 0.5V,

the HY29F080 will be in the RESET# TTL Standby

mode, but the standby current will be greater. See

Hardware Reset Operation section for additional

information on the reset operation.

The device requires standard access time (t

CE) for

read access when the device is in either of the

standby modes, before it is ready to read data. If

the device is deselected during erasure or pro-

gramming, it continues to draw active current until

the operation is completed.

Hardware Reset Operation

The RESET# pin provides a hardware method of

resetting the device to reading array data. When

the RESET# pin is driven Low for the minimum

specified period, the device immediately termi-

nates any operation in progress, tri-states the data

bus pins, and ignores all read/write commands for

the duration of the RESET# pulse. The device also

resets the internal state machine to reading array

data. If an operation was interrupted by the as-

sertion of RESET#, it should be reinitiated once

the device is ready to accept another command

sequence to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse as described in the Standby Operation sec-

tion above.

If RESET# is asserted during a program or erase

operation (RY/BY# pin is Low), the internal reset

operation is completed within a time of t

READY (during

Automatic Algorithms). The RY/BY# pin will go High

during the t

READY interval, and the system can per-

form a read or write operation after waiting for a mini-

mum of t

READY or until tRH after the RESET# pin re-

turns High, whichever is longer. If RESET# is as-

serted when a program or erase operation is not

executing (RY/BY# pin is High), the reset operation

is completed within a time of t

RP. In this case, the

host can perform a read or write operation t

RH after

the RESET# pin returns High.

The RESET# pin may be tied to the system reset

signal. Thus, a system reset would also reset the

device, enabling the system to read the boot-up

firmware from the Flash memory.

Sector Group Protect/Unprotect Operations

Hardware sector group protection can be invoked

to disable program and erase operations in any

single sector group or combination of sector

groups. This function is typically used to protect

data in the device from unauthorized or acciden-

tal attempts to program or erase the device while

it is in the system (e.g., by a virus) and is imple-

mented using programming equipment. Sector

group unprotection re-enables the program and

erase operations in previously protected sectors.

Table 1 identifies the eight sector groups and the

address ranges that each covers. The device is

shipped with all sector groups unprotected.

The sector group protect/unprotect operations re-

quire a high voltage (V

ID) on address pin A9 and

the CE# and/or OE# control pins, as detailed in

Table 3. When implementing these operations,

note that V

CC must be applied to the device before

applying V

ID, and that VID should be removed be-

fore removing V

CC from the device.

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