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Bit 12 — PCTE

Bit [11:8] — PDC3 - PDC0

Bit [7:4] — A3 - A0

Bit [3:0] — N3 - N0

OUT +

MCLK

(4N ) A)

, (N w A),

MCLK

u 1MHz

(3)

TSC2301

SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004

PLL Control Enable. This bit allows the user to manually control the audio codec internal PLL. This allows the

user to modify the contents of bits [11-0] to control the audio codec PLL. Writing a 0 to this bit enables manual

control of the PLL. Otherwise, the PLL is set automatically based on the settings of MCLK [1:0] and I2SFS[3:0] in

the audio control register (bits 7-2 in register 00h, page 2).

Table 27. PLL Control Enable

PLLO

Description

Allows modification of bits [11:0].

PLL operates as normal, no manual override (default).

PLL Predivider Control. This bit controls the predivider to the internal PLL. These bits represent a 4-bit straight

binary number corresponding to the variable P in the PLL control equation discussed later in this section. The

legal range of these bits is 1h to Fh. The default of these bits is Fh.

A Control. This bit represent a 4-bit straight binary number corresponding to the variable A in the PLL control

equation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.

N Control. This bit represents a 4-bit straight binary number corresponding to the variable N in the PLL control

equation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.

When using a nonaudio standard MCLK frequency or crystal that is not covered by any of the automatic PLL

settings in MCLK[1:0], the user must manually configure the TSC2301 PLL to generate the proper clock for the

audio data converters. The proper clock for any sampling rates that are submultiples of 44.1 kHz is 512 x 44.1

kHz = 22.5792 MHz. This frequency is valid for 44.1 kHz, 22.05 kHz, and 11.025 kHz. The proper clock for any

sampling rates that are submultiples of 48 kHz is 512 x 48 kHz = 24.576 MHz. This frequency is valid for 48 kHz,

32 kHz, 24 kHz, 16 kHz, 12 kHz, and 8 kHz. Equation 3 is used to obtain the proper frequency. Since variables

P, N, and A are integers, the exact proper clock frequencies can not always be obtained. However, examples are

provided for common MCLK/crystal frequencies that minimize the error of the PLL output. One constraint is the N

must always be greater than or equal to A. Another constraint is that the output of the MCLK predivider (the

MCLK/P term) should be greater than 1 MHz. P can be any integer from 1 to 15, inclusive. N and A can be any

integer from 0 to 15, inclusive. In some situations, settings outside of these constraints may work, but should be

verified by the user beforehand. Table 28 shows some settings that have been tested and confirmed to work by

TI.

Table 28. PLL Settings

MCLK (MHz)

Desired

Actual Fout(MHz)

% Error

Fout(MHz)

24.576

24.57143

-0.019

24.576

24.55556

-0.083

24.576

24.61538

0.160

19.2

24.576

24.61538

0.160

19.68

24.576

24.60000

0.097

3.6869

22.5792

22.53106

-0.213

22.5792

22.54545

-0.149

22.5792

22.59524

0.071

22.5792

22.56410

-0.067

19.2

22.5792

22.61333

0.151

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