ADF4356BCPZ datasheet(5/35 Pages) AD

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Data Sheet

ADF4356

Rev. 0 | Page 5 of 35

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Normalized In-Band Phase Noise Floor

Fractional Channel5

−225

dBc/Hz

Integer Channel6

−227

dBc/Hz

Normalized 1/f Noise, PN1_f7

−121

dBc/Hz

10 kHz offset; normalized to 1 GHz

Integrated RMS Jitter (1 kHz to 20 MHz)8

Spurious Signals Due to PFD Frequency

−85

dBc

VCP is the voltage at the CPOUT pin.

IOL is the output low current.

TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.

RF output power using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. Unused RF output pins are terminated in 50 Ω.

Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−225 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.

Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−227 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)

and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the

ADIsimPLL design tool.

Integrated RMS jitter using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. The EV-ADF4356SD1Z evaluation board is configured to

accept a single ended REFIN (SMA 100) = 160 MHz, VCO frequency = 6 GHz, PFD frequency = 80 MHz, charge pump current = 0.9 mA, and bleed current is off. The loop

filter is configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated in 50 Ω.

TIMING CHARACTERISTICS

AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred

to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.

Table 2. Write Timing

Parameter

Limit

Unit

Description

fCLK

MHz max

Serial peripheral interface CLK frequency

ns min

LE setup time

ns min

DATA to CLK setup time

ns min

DATA to CLK hold time

ns min

CLK high duration

ns min

CLK low duration

ns min

CLK to LE setup time

20 or (2/fPFD),

whichever is longer

ns min

LE pulse width

Write Timing Diagram

CLK

DATA

DB31 (MSB)

DB30

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB2

(CONTROL BIT C3)

DB3

(CONTROL BIT C4)

Figure 2. Write Timing Diagram

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