Serially Controlled, 1.5 Ω, On-Resistance,

High Voltage, iCMOS, Quad SPST Switch

Data Sheet

ADGS1412

Rev. 0

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FEATURES

SPI interface with error detection

Includes CRC, invalid read/write address, and SCLK count

error detection

Supports burst and daisy-chain mode

Industry-standard SPI Mode 0 and Mode 3 interface-

compatible

1.5 Ω typical on resistance at 25°C

0.3 Ω typical on-resistance flatness at 25°C

0.1 Ω typical on-resistance match between channels at 25°C

Fully specified at ±15 V, ±5 V, and +12 V

APPLICATIONS

Automated test equipment

Data acquisition systems

Battery-powered systems

Sample-and-hold systems

Audio signal routing

Video signal routing

Communications systems

Relay replacement

FUNCTIONAL BLOCK DIAGRAMS

S4

S3

S2

S1

D4

SDO

SCLK SDI

CS

D3

D2

D1

ADGS1412

SPI

INTERFACE

Figure 1.

GENERAL DESCRIPTION

The ADGS1412 contains four independent single-pole/single-

throw (SPST) switches. An serial peripheral interface (SPI)

controls the switches. The SPI interface has robust error detection

features such as cyclic redundancy check (CRC) error detection,

invalid read/write address detection, and SCLK count error

detection.

It is possible to daisy-chain multiple ADGS1412 devices together.

Daisy-chain mode enables the configuration of multiple devices

with a minimal amount of digital lines. The ADGS1412 can also

operate in burst mode to decrease the time between SPI

commands.

iCMOS construction ensures ultralow power dissipation, making

the device ideally suited for portable and battery-powered

instruments.

Each switch conducts equally well in both directions when on,

and each switch has an input signal range that extends to the

supplies. In the off condition, signal levels up to the supplies

are blocked.

The on-resistance profile is flat over the full analog input range,

which ensures good linearity and low distortion when switching

audio signals.

PRODUCT HIGHLIGHTS

1.

SPI interface removes the need for parallel conversion,

logic traces and reduces GPIO channel count.

2.

Daisy-chain mode removes additional logic traces when

multiple devices are used.

3.

CRC error detection, invalid read/write address detection,

and SCLK count error detection ensures a robust digital

interface.

4.

Safety integrity level (SIL)-compatible.

5.

Minimum distortion.