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ADGS1412BCPZ Datasheet(PDF) 9 Page - Analog Devices

Part # ADGS1412BCPZ
Description  Serially Controlled, 1.5 廓, On-Resistance, High Voltage, iCMOS, Quad SPST Switch
PDF  26 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADGS1412BCPZ Datasheet(HTML) 9 Page - Analog Devices

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ADGS1412
Data Sheet
Rev. 0 | Page 8 of 25
Parameter
Limit
Unit
Test Conditions/Comments
t7
10
ns min
SCLK active edge to CS rising edge
t8
20
ns max
CS falling edge to SDO data available
t91
20
ns max
SCLK falling edge to SDO data available
t10
20
ns max
CS rising edge to SDO returns to high impedance
t11
20
ns min
CS high time between SPI commands
t12
8
ns min
CS falling edge to SCLK becomes stable
t13
8
ns min
CS rising edge to SCLK becomes stable
1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams
t1
t2
t3
t4
t5
t8
t9
t10
t6
t7
R/W
CS
SCLK
SDI
SDO
A6
A5
D2
D1
D0
00
1
D2
D1
D0
Figure 2. Address Mode Timing Diagram
t1
t2
t3
t4
t5
t8
t9
t10
t6
t7
CS
SCLK
SDI
SDO
INPUT BYTE FOR DEVICE N
INPUT BYTE FOR DEVICE N + 1
ZERO BYTE
INPUT BYTE FOR DEVICE N
D7
D6
D0
D7
D6
D1
D0
0
0
0
D7D6
D1D0
Figure 3. Daisy Chain Timing Diagram
t13
t11
t12
CS
SCLK
Figure 4. SCLK/CS Timing Relationship



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