P89682K datasheet(13/44 Pages) APLUS

13 / 44 page

Integrated Circuits Inc.

aP89682K/341K/170K/085K

Ver 2.5.1

May 24 2016

State Description :

State Name

Description

Reset

Include Power On Reset (typ 5us) and external reset (depends on the external reset circuit).

All pins are input floating.

Serial Command inhibited.

After reset, state transfer to the " Configure " state.

Configure

Internal Chip Configuration.

All pins are input floating.

Serial Command inhibited. (Max configure time = 2ms)

After configuration, state transfer to the "Idle" state.

Idle

State transfer to the "Play" state if "active command" received before timeout.

After time out without active command, state transition to the "Sleep" State.

Play

Playing Voice Group include ramp.

State transfer to the "Wait" state if nothing to be played.

Wait

Wait new Serial command and back to the play state without time limit.

State transition to the "Sleep" state if "de-active command" received.

Ramp down before transition to the sleep if the "PD2" command be accepted.

Sleep

State transition to the "Wakeup" state if selected by the host CPU.

(Wait sleep to wake up state time = 20us.)

Wakeup

Single command be buffered and wait to execute after wakeup state!!

(Max wakeup time = 2ms).

State transition to the "Play" state if active command received else to the "Idle" state.

Fig. 9 State Description

*** Active commands are "Load", "Play", "PU1" and "PU2".

De-Active commands are "PD1" and "PD2".

In CPU Serial Command Control :

a. Using PU1/PU2 command first from de-active state.

Add 2ms delay after PU1/PU2 command is necessary.

b. Max "Output Delay of Busy/Full Signal" equal 2ms during active.

c. OUT2's select is different from the aP89xxx Series. ( POUT)

Output select to reference PIN DESCRIPTIONS of OUT1、OUT2 and OUT3.

P89682K Datasheet(PDF) 13 Page - Aplus Intergrated Circuits

P89682K Datasheet(HTML) 13 Page - Aplus Intergrated Circuits

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