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P89682K Datasheet(PDF) 14 Page - Aplus Intergrated Circuits

Part # P89682K
Description  VOICE OTP IC
PDF  44 Pages
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Manufacturer  APLUS [Aplus Intergrated Circuits]
Direct Link  http://www.aplusinc.com.tw
Logo APLUS - Aplus Intergrated Circuits

P89682K Datasheet(HTML) 14 Page - Aplus Intergrated Circuits

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Integrated Circuits Inc.
aP89682K/341K/170K/085K
Ver 2.5.1
14
May 24 2016
aP89 Mode :
This trigger mode is function setting similar with APLUS 1st Generation OTP IC
(aP89341/aP89170/aP89085 ).
In aP89 Mode Operating Mode Setting:
M1=0, M0=0 set the chip into Key Trigger Mode.
It operates to reference Key Mode.
M1=0, M0=1 set the chip into CPU Parallel Command Mode.
It operates to reference CPU Parallel Mode.
M1=1, M0=0 set the chip into CPU Serial Command Mode.
The CPU serial command compatible with APLUS 1st Generation OTP IC.
It is controlled by command sent to it from the host CPU.S1 to S3 are used to input command word
into the chip while OUT1 to OUT3 as output from the chip to the host CPU for feedback response.
-
S1 acts as CS (Chip Select) to initiate the command word input
-
S2 acts as SCK (Serial Clock) to clock-in the command word at rising edge.
-
S3 acts as DI (Data-In) to input the command bits.
-
OUT1 acts as BUSY to indicate the chip is in busy state(include play and ramp).
-
OUT2 acts as OUT function to output user selected information.
-
OUT3 acts as Load signal to indicate the Voice Group address buffer is full and waiting for play.
aP89Mode -CPU Serial Command Table [LSB First, Command Byte First]:
Fig. 10 aP89Mode CPU Serial Command Table
D7
D6
D5
D4
D3
D2
D1
D0
G7
G6
G5
G4
G3
G2
G1
G0
PREFETCH
0
1
1
1
0
0
0
1
Voice Group Address Number
PLAY
0
1
0
1
0
1
0
1
Voice Group Address Number
PU1 w/o Ramp
1
1
0
0
0
1
0
1
None
PU2 with Ramp
1
0
0
0
1
1
0
1
None
PD1 w/o Ramp
1
1
1
0
0
0
0
1
None
PD2 with Ramp
1
0
1
0
1
0
0
1
None
VOL
1
0
1
1
0
0
1
0
0
0
0
0
VOL[3:0]
VOL--
1
0
1
1
0
0
0
1
None
VOL++
1
0
1
1
0
1
0
0
None
PAUSE
0
0
1
1
1
0
0
1
None
RESUME
0
0
0
1
1
1
0
1
None



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