Preliminary

Avance Logic, Inc.

ALC202

- 12 -

Rev0.62

http://www.realtek.com.tw

MX26

Powerdown Control/Status

Default: 000FH

Bit

Type

Function

15

R/W PR7 External Amplifier Power Down (EAPD) 0: normal 1: Power down

14

R/W PR6 0: Normal 1: Power down Headphone Out (HP-OUT)

13

R/W PR5 0: Normal 1: Disable internal clock

12

R/W PR4 0: Normal 1: Power down AC-Link

11

R/W PR3 0: Normal 1: Power down Mixer (Vref off)

10

R/W PR2 0: Normal 1: Power down Mixer (Vref still on)

9

R/W PR1 0: Normal 1: Power down PCM DAC

8

R/W PR0 0: Normal 1: Power down PCM ADC and input MUX

7:4

Reserved, Read as 0

3

R

Vref status 1: Vref is up to normal level 0: Not yet

2

R

Analog Mixer status 1: Ready 0: Not yet

1

R

DAC status 1: Ready 0: Not yet

0

R

ADC status 1: Ready 0: Not yet

MX28

Extended Audio ID

Default: 060Fh

Bit

Type

Function

15

R

ID1 Ê

14

R

ID0

13:12

Reserved, Read as 0

11:10

R

REV[1:0]=01 to indicates ALC202 is AC’97 rev2.2 compliant.

9

R

AMAP read as 1 (DAC mapping based on ID)

8:6

Reserved, Read as 0

5:4

R/W DSA[1:0], DAC Slot AssignmentË (Default value depends on ID[1:0])

DSA[1:0] control DAC slot assignment described in AC’97 rev2.2.

3

Reserved, Read as 0

2

R

SPDIF read as 1 (S/PDIF is supported)

1

R

DRA read as 1

0

R

VRA read as 1 (Variable Rate Audio is supported)

Ê

ID1 is latched inversely from pin 46 when system reset. ID0 is latched inversely from pin 45

when system reset.

Ë

ALC202 maps DAC slot according to the following table: (default maps to AC’97 spec.

rev2.2)

DSA[1:0]

Left DAC slot #

Right DAC slot #

Comment

0,0

3

4

Default when ID[1:0]=00

0,1

7

8

Default when ID[1:0]=01,10

1,0

6

9

Default when ID[1:0]=11

1,1

10

11

MX2A

Extended Audio Status and control register

Default: 0000H

Bit

Type

Function

15:11

Reserved

10

R

SPCV (S/PDIF Configuration Valid)

0: current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid.

1: current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid.

9:6

Reserved

5:4

R/W SPSA[1:0] (S/PDIF Slot Assignment)

00: S/PDIF source data assigned to AC-LINK slot3/4.

01: S/PDIF source data assigned to AC-LINK slot7/8.

10: S/PDIF source data assigned to AC-LINK slot6/9.