DS2196L datasheet(83/157 Pages) DALLAS

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DS2196

83 of 157

RSCD2A: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER A

(Address = 1C Hex)

RSCD2B: RECEIVE SPARE CODE DEFINITION REGISTER 2 FRAMER B

(Address = BC Hex)

(MSB)

(LSB)

SYMBOL

POSITION

NAME AND DESCRIPTION

RSCD2.7

Receive Spare Code Definition Bit 7. A Don’t Care if a 1 to

7 bit length is selected.

RSCD2.6

Receive Spare Code Definition Bit 6. A Don’t Care if a 1 to

7 bit length is selected.

RSCD2.5

Receive Spare Code Definition Bit 5. A Don’t Care if a 1 to

7 bit length is selected.

RSCD2.4

Receive Spare Code Definition Bit 4. A Don’t Care if a 1 to

7 bit length is selected.

RSCD2.3

Receive Spare Code Definition Bit 3. A Don’t Care if a 1 to

7 bit length is selected.

RSCD2.2

Receive Spare Code Definition Bit 2. A Don’t Care if a 1 to

7 bit length is selected.

RSCD2.1

Receive Spare Code Definition Bit 1. A Don’t Care if a 1 to

7 bit length is selected.

RSCD2.0

Receive Spare Code Definition Bit 0. A Don’t Care if a 1 to

7 bit length is selected.

13.

CLOCK BLOCKING REGISTERS

The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking

Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.

The

RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during

individual channels. These outputs can be used to block clocks to a UART or LAPD controller in

Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a 1, the RCHBLK and

TCHBLK pins will be held high during the entire corresponding channel time. See the timing in

Section 21 for an example.

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