DS2196L datasheet(89/157 Pages) DALLAS

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DS2196

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Table 15-1: BERT PATTERN SELECT OPTIONS

PS2

PS1

PS0

Pattern Definition

000

Pseudorandom 2E7 – 1

001

Pseudorandom 2E11 – 1

010

Pseudorandom 2E15 – 1

011

Pseudorandom Pattern QRSS. A 220 - 1 pattern with 14

consecutive zero restriction.

100

Repetitive Pattern

101

Alternating Word Pattern

110

Modified 55 Octet (Daly) Pattern The Daly pattern is a

repeating 55 octet pattern that is byte aligned into the active

DS0 timeslots. The pattern is defined in a ATIS (Alliance

for Telecommunications Industry Solutions) Committee T1

Technical Report Number 25 (November 1993).

111

Reserved

BC1: BERT Control Register 1 (Address = 41 Hex)

(MSB)

(LSB)

IESYNC

IEBED

IEOF

–

RPL3

RPL2

RPL1

RPL0

SYMBOL

POSITION

NAME AND DESCRIPTION

IESYNC

BC1.7

Change of Synchronization Status Interrupt Enable.

Interrupt enable for Synchronizer Status (BIR.0)

0 = interrupt masked

1 = interrupt enabled

IEBED

BC1.6

Bit Error Detected Interrupt Enable. Interrupt enable for Bit

Error Detected (BIR.3)

0 = interrupt masked

1 = interrupt enabled

IEOF

BC1.5

Bit & Error Counter Overflow Interrupt Enable. Interrupt

enable for the BERT Bit Counter (BIR.2) and BERT Error

Counter (BIR.1) overflow.

0 = interrupt masked

1 = interrupt enabled

–

BC1.4

Not Assigned. Should be set to 0 when written to.

RPL3

BC1.3

Repetitive Pattern Length Bit 3 (RPL3). Refer to Table 15-2

for details.

RPL2

BC1.2

Repetitive Pattern Length Bit 2 (RPL2). Refer to Table 15-2

for details.

RPL1

BC1.1

Repetitive Pattern Length Bit 1 (RPL1). Refer to Table 15-2

for details.

RPL0

BC1.0

Repetitive Pattern Length Bit 0 (RPL0). Refer to Table 15-2

for details.

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