AD7779ACPZ datasheet(39/101 Pages) AD

39 / 101 page

AD7779

Data Sheet

Rev. A | Page 38 of 100

There are two different ways to achieve a synchronous pulse if

the controller/processor cannot generate it, as follows:



Applying an asynchronous pulse on the START pin, which

is then internally synchronized with the external MCLK

clock, and the resulting synchronous signal is output on

the SYNC_OUT pin.



Triggering the SYNC_OUT internally. When the AD7779

is configured in SPI control mode, toggling Bit 0 in the

GEN_USER_CONFIG_2 register generates a synchronous

pulse that is output on the SYNC_OUT pin.

The SYNC_IN and SYNC_OUT pins must be externally

connected if internal synchronization is used.

If multiple AD7779 devices must be synchronized, the

SYNC_OUT pin of one device can be connected to multiple

devices. This synchronization method requires the use of a

common MCLK signal for all the AD7779 devices connected,

as shown in Figure 94.

If the START pin is not used, tie it to DGND.

START

SYNC_IN

MCLK

SYNC_OUT

START

SYNC_IN

MCLK

SYNC_OUT

START

SYNC_IN

MCLK

SYNC_OUT

AD7779

SYNCHRONIZATION

LOGIC

ASYNCHRONOUS

PULSE

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MCLK

Figure 94. Multiple AD7779 Synchronization

DIGITAL FILTERING

The AD7779 offers a low latency sinc3 filter. Most precision

Σ-Δ ADCs use sinc3 filters because the sinc3 filter offers a low

latency path for applications requiring low bandwidth signals,

for example, in control loops or where application specific

postprocessing is required. The digital filter adds notches at

multiples of the sampling frequency.

The digital filter implements three main notches, one at the

maximum ODR (16 kHz or 8 kHz, depending on the power

mode) and another two at the ODR frequency selected to stop

noise aliasing into the pass band.

Figure 95 shows the typical filter transfer function for the high

resolution and low power modes using a decimation rate of

256 samples.

FREQUENCY (kHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

LOW POWER MODE DECIMATION = 256

HIGH RESOLUTION MODE DECIMATION = 256

Figure 95. Sinc3 Frequency Response

The sample rate converter featured allows fine tuning of the

decimation rate, even for noninteger multiples of the decimation

rate. See the Sample Rate Converter (SRC) section for more

information on filter profiles for noninteger decimation rates.

SHUTDOWN MODE

The AD7779 can be placed in shutdown mode by pulling

AVDD2 to ground and connecting 1 MΩ resistance, pulled low,

to XTAL2. In this mode, the average current consumption is

reduced to 1 mA, as shown in Figure 96.

–40

–0.5

0.5

1.0

TEMPERATURE (°C)

125

IAVDD1x

IAVDD2x

IAVDD4x

IIOVDD

AVDDx = 3.3V

IOVDD = 3.3V

Figure 96. Shutdown Current

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