AD7779ACPZ datasheet(43/101 Pages) AD

43 / 101 page

AD7779

Data Sheet

Rev. A | Page 42 of 100

SPI Control Functionality

Global Control Functions

The following list details the global control functions of the

AD7779:

•

High resolution and low power modes of operation

•

Output data rate: sample rate converter (SRC)

•

VCM buffer power-down

•

Internal/external reference selection

•

Enable, precharged, or bypassed reference buffer modes

•

Internal reference power-down

•

SAR diagnostic mux

•

SAR power-down

•

GPIO write/read

•

SPI SAR conversion readback

•

SPI slave mode—read Σ-∆ results

•

SDO and DOUT drive strength

•

DOUT mode

•

DCLK division

•

Internal LDO bypassed

•

CRC protection: enabled or disabled

Per Channel Functions

The following list details the per channel functions of the

AD7779:

•

PGA gain.

•

Σ-∆ channel power-down.

•

Phase delay: synchronization phase offset per channel.

•

Calibration of offset.

•

Calibration of gain.

•

Σ-∆ input signal mux.

•

Channel error register.

•

PGA gain.

Phase Adjustment

The AD7779 phase delay can be adjusted to compensate for phase

mismatches between channels due to sensors or signal channel

phase errors connected to the AD7779. Achieve phase adjustment

by programming the CHx_SYNC_OFFSET register. This

programming delays the synchronization signal by a certain

number of modulator clocks, MOD_CLKs, to individually initiate

the digital filter for each Σ-∆ ADC.

The phase adjustment register is read during the pulse; conse-

quently, any further changes on the register have no effect unless a

pulse is generated (see the Digital Reset and Synchronization

Pins section for more information on how to generate a pulse in

the pin).

The phase offset register is multiplied internally by a factor that

depends on the decimation rate, as shown in Table 20.

Table 20. Phase Adjustment vs. Decimation Rate

Phase Adjustment Compensation

Decimation Rate

×1

≤255

×2

≤511

×4

≤1023

×8

≤2047

×16

≤4095

The maximum phase delay cannot be equal to or greater than

the decimation rate. If this is the case, the value changes

internally to the decimation rate value minus 1.

As an example, the phase mismatch between Channel 0 and

Channel 1 is 5°, and the ODR is 5 kSPS in high resolution mode. In

this case, the decimation rate is 2048 kHz/5 kHz = 409.6, which

means that the offset register value is multiplied internally by 2.

Assuming an input signal of 50 Hz, the number of MOD_

MCLK pulses required to sample a full period is 2048 kHz/

50 Hz = 40960 > 360°/40960 = 0.00878°.

If a 5° delay is required, the number of MOD_MCLK delays

must be 569 (5°/0.00878°) because the offset register is multiplied

by 2; the final offset register value is 409.6/2 − 569/2, which

gives a negative value. In this case, if the offset value programmed

to the register is higher than 204 (for example, 210 × 2 = 420),

the value is internally changed to 408, resulting in a phase

compensation of 408 × 0.00878° = 3.58°.

PGA Gain

The PGA gain can be selected individually by appropriately

selecting Bits[7:6] in the CHx_CONFIG register, as shown in

Table 21.

Table 21. PGA Gain Settings via CHx_CONFIG

CHx_CONFIG, Bits[7:6] Setting

PGA Gain Setting

×1

×2

×4

×8

If the Σ-∆ reference is updated, it is recommended to apply a

pulse on the SYNC_IN pin to remove invalid samples during

the transition of the reference

Decimation

The decimation defines the sampling frequency as follows:

•

In high resolution mode, the sampling frequency = MCLK/

(4 × decimation)

•

In low power mode, the sampling frequency = MCLK/

(8 × decimation)

Refer to the Sample Rate Converter (SRC) section for more

information.

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