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MPC855 Datasheet(PDF) 35 Page - Motorola, Inc |
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MPC855 Datasheet(HTML) 35 Page - Motorola, Inc |
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35 / 76 page  MOTOROLA MPC860 Family Hardware Specifications 35 Bus Signal Timing Figure 9-24 provides the PCMCIA access cycle timing for the external bus read. Figure 9-24. PCMCIA Access Cycles Timing External Bus Read Figure 9-25 provides the PCMCIA access cycle timing for the external bus write. 1 PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC860 PowerQUICC User s Manual. CLKOUT A[0:31] REG CE1/CE2 PCOE, IORD TS D[0:31] ALE B19 B18 P53 P52 P52 P51 P50 P48 P49 P46 P45 P44 P47 |
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