MPC855 datasheet(50/76 Pages) MOTOROLA

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MPC860 Family Hardware Speciﬁcations

MOTOROLA

Serial Interface AC Electrical Specifications

Figure 11-49. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

L1RCLK, L1TCLK width low (DSC =1)

P + 10

—

83a

L1RCLK, L1TCLK width high (DSC = 1)3

P + 10

—

L1CLK edge to L1CLKO valid (DSC = 1)

—

30.00

L1RQ valid before falling edge of L1TSYNC4

1.00

—

L1TCL

L1GR setup time2

42.00

—

L1GR hold time

42.00

—

L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,

DSC = 0)

—

0.00

1 The ratio SYNCCLK/L1RCLK must be greater than 2.5/1.

2 These specs are valid for IDL mode only.

3 Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.

4 These strobes and TxD on the ﬁrst bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.

Table 11-17. SI Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

L1RXD

(Input)

L1RCLK

(FE=0, CE=0)

(Input)

L1RCLK

(FE=1, CE=1)

(Input)

L1RSYNC

(Input)

L1ST(4-1)

(Output)

71a

RFSD=1

BIT0

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