PCI7621 datasheet(74/298 Pages) TI

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3−18

Table 3−11. PC Card Interrupt Events and Description

CARD TYPE

EVENT

TYPE

SIGNAL

DESCRIPTION

Battery conditions

CSC

BVD1(STSCHG)//CSTSCHG

A transition on BVD1 indicates a change in the

PC Card battery conditions.

16-bit

memory

Battery conditions

(BVD1, BVD2)

CSC

BVD2(SPKR)//CAUDIO

A transition on BVD2 indicates a change in the

PC Card battery conditions.

memory

Wait states

(READY)

CSC

READY(IREQ)//CINT

A transition on READY indicates a change in the

ability of the memory PC Card to accept or provide

data.

16-bit I/O

Change in card

status (STSCHG)

CSC

BVD1(STSCHG)//CSTSCHG

The assertion of STSCHG indicates a status change

on the PC Card.

16-bit I/O/

UltraMedia

Interrupt request

(IREQ)

Functional

READY(IREQ)//CINT

The assertion of IREQ indicates an interrupt request

from the PC Card.

CardBus

Change in card

status (CSTSCHG)

CSC

BVD1(STSCHG)//CSTSCHG

The assertion of CSTSCHG indicates a status

change on the PC Card.

CardBus

Interrupt request

(CINT)

Functional

READY(IREQ)//CINT

The assertion of CINT indicates an interrupt request

from the PC Card.

All PC Cards/

Smart Card

adapters/

Card insertion

or removal

CSC

CD1//CCD1,

CD2//CCD2

A transition on either CD1//CCD1 or CD2//CCD2

indicates an insertion or removal of a 16-bit or

CardBus PC Card.

adapters/

UltraMedia/

Flash Media

Power cycle

complete

CSC

N/A

An interrupt is generated when a PC Card power-up

cycle has completed.

The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For

example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for

CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in

parentheses. The CardBus signal name follows after a double slash (//).

The 1997 PC Card Standard describes the power-up sequence that must be followed by the PCI7x21/PCI7x11

controller when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon

completion of this power-up sequence, the PCI7x21/PCI7x11 interrupt scheme can be used to notify the host system

(see Table 3−11), denoted by the power cycle complete event. This interrupt source is considered a PCI7x21/PCI7x11

internal event, because it depends on the completion of applying power to the socket rather than on a signal change

at the PC Card interface.

3.7.2

Interrupt Masks and Flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−11 by setting

the appropriate bits in the PCI7x21/PCI7x11 controller. By individually masking the interrupt sources listed, software

can control those events that cause a PCI7x21/PCI7x11 interrupt. Host software has some control over the system

interrupt the PCI7x21/PCI7x11 controller asserts by programming the appropriate routing registers. The

PCI7x21/PCI7x11 controller allows host software to route PC Card CSC and PC Card functional interrupts to separate

system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more

detail in the following sections.

When an interrupt is signaled by the PCI7x21/PCI7x11 controller, the interrupt service routine must determine which

of the events listed in Table 3−10 caused the interrupt. Internal registers in the PCI7x21/PCI7x11 controller provide

flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine

the action to be taken.

Table 3−10 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can

be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Notice that there is not a mask bit to stop the PCI7x21/PCI7x11 controller from passing PC Card functional interrupts

through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and

there must never be a card interrupt that does not require service after proper initialization.

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