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PCI7621 Datasheet(PDF) 15 Page - Texas Instruments |
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PCI7621 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 298 page  xv Table Title Page 5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description 5−20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−14 ExCA Card Detect and General Control Register Description 5−21 . . . . . . . . . 5−15 ExCA Global Control Register Description 5−22 . . . . . . . . . . . . . . . . . . . . . . . . . 6−1 CardBus Socket Registers 6−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2 Socket Event Register Description 6−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−3 Socket Mask Register Description 6−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4 Socket Present State Register Description 6−4 . . . . . . . . . . . . . . . . . . . . . . . . . 6−5 Socket Force Event Register Description 6−6 . . . . . . . . . . . . . . . . . . . . . . . . . . 6−6 Socket Control Register Description 6−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7 Socket Power Management Register Description 6−8 . . . . . . . . . . . . . . . . . . . 7−1 Function 2 Configuration Register Map 7−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−2 Command Register Description 7−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−3 Status Register Description 7−4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−4 Class Code and Revision ID Register Description 7−5 . . . . . . . . . . . . . . . . . . . 7−5 Latency Timer and Class Cache Line Size Register Description 7−5 . . . . . . . 7−6 Header Type and BIST Register Description 7−6 . . . . . . . . . . . . . . . . . . . . . . . . 7−7 OHCI Base Address Register Description 7−6 . . . . . . . . . . . . . . . . . . . . . . . . . . 7−8 TI Base Address Register Description 7−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−9 CardBus CIS Base Address Register Description 7−8 . . . . . . . . . . . . . . . . . . . 7−10 Subsystem Identification Register Description 7−9 . . . . . . . . . . . . . . . . . . . . . . 7−11 Interrupt Line Register Description 7−10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−12 PCI Interrupt Pin Register—Read-Only INTPIN Per Function 7−10 . . . . . . . . . 7−13 Minimum Grant and Maximum Latency Register Description 7−11 . . . . . . . . . 7−14 OHCI Control Register Description 7−11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−15 Capability ID and Next Item Pointer Registers Description 7−12 . . . . . . . . . . . . 7−16 Power Management Capabilities Register Description 7−13 . . . . . . . . . . . . . . . 7−17 Power Management Control and Status Register Description 7−14 . . . . . . . . . 7−18 Power Management Extension Registers Description 7−14 . . . . . . . . . . . . . . . . 7−19 PCI PHY Control Register Description 7−15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7−20 PCI Miscellaneous Configuration Register Description 7−16 . . . . . . . . . . . . . . . 7−21 Link Enhancement Control Register Description 7−17 . . . . . . . . . . . . . . . . . . . . 7−22 Subsystem Access Register Description 7−18 . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1 OHCI Register Map 8−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−2 OHCI Version Register Description 8−4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−3 GUID ROM Register Description 8−5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−4 Asynchronous Transmit Retries Register Description 8−6 . . . . . . . . . . . . . . . . 8−5 CSR Control Register Description 8−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−6 Configuration ROM Header Register Description 8−8 . . . . . . . . . . . . . . . . . . . . 8−7 Bus Options Register Description 8−9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−8 Configuration ROM Mapping Register Description 8−11 . . . . . . . . . . . . . . . . . . . 8−9 Posted Write Address Low Register Description 8−11 . . . . . . . . . . . . . . . . . . . . 8−10 Posted Write Address High Register Description 8−12 . . . . . . . . . . . . . . . . . . . . |
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