A3G4250D datasheet(33/44 Pages) STMICROELECTRONICS

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A3G4250D

Doc 022768 Rev 3

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7.4

CTRL_REG3 (22h)

7.5

CTRL_REG4 (23h)

Reference signal for filtering

Normal mode

Auto-reset on interrupt event

Table 27.

High-pass filter cut-off frequency configuration [Hz]

HPCF3

ODR= 100 Hz

ODR= 200 Hz

ODR= 400 Hz

ODR= 800 Hz

0000

0001

0010

0011

0100

0.5

0101

0.2

0.5

0110

0.1

0.2

0.5

0111

0.05

0.1

0.2

0.5

1000

0.02

0.05

0.1

0.2

1001

0.01

0.02

0.05

0.1

Table 26.

High-pass filter mode configuration

Table 28.

CTRL_REG1 register

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Table 29.

CTRL_REG3 description

I1_Int1

Interrupt enable on the INT1 pin. Default value 0. (0: disable; 1: enable)

I1_Boot

Boot status available on INT1. Default value 0. (0: disable; 1: enable)

H_Lactive

Interrupt active configuration on INT1. Default value 0. (0: high; 1: low)

PP_OD

Push-pull / open drain. Default value: 0. (0: push-pull; 1: open drain)

I2_DRDY

Date ready on DRDY/INT2. Default value 0. (0: disable; 1: enable)

I2_WTM

FIFO watermark interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)

I2_ORun

FIFO overrun interrupt on DRDY/INT2 Default value: 0. (0: disable; 1: enable)

I2_Empty

FIFO empty interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)

Table 30.

CTRL_REG4 register

0BLE

ST1

ST0

SIM

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