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PC87311AVF Datasheet(PDF) 54 Page - National Semiconductor (TI) |
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PC87311AVF Datasheet(HTML) 54 Page - National Semiconductor (TI) |
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54 / 78 page  60 Serial Ports (Continued) This is a read and write register Table 6-7 shows the con- tents of the LCR Details on each bit follow TLF11362 – 14 FIGURE 6-2 PC87312 Composite Serial Data Bits 0 1 These two bits specify the number of data bits in each transmitted or received serial character The encoding of bits 0 and 1 is as follows Bit 1 Bit 0 Data Length 0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits TABLE 6-7 PC87312 Register Summary for an Individual UART Channel Register Address 0DLABe0 0DLABe0 1DLABe0 2 2 3 4 5 6 7 0DLABe1 1DLABe1 No Bit Receiver Register Buffer (Read Only) Transmitter Register Holding (Write Only) Interrupt Register Enable Interrupt Register (Read Ident Only) Register Control (Write Only) FIFO Register Control Line Register MODEM Control Register Status Line Register MODEM Status Register Scratch Pad (LS) (MS) RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM 0 Data Bit 0 Data Bit 0 Enable ‘‘0’’ if FIFO Word Data Data Delta Bit 0 Bit 0 Bit 8 (Note 1) Received Interrupt Enable Length Terminal Ready Clear Data Pending Select Ready (DR) to Send Available Bit 0 (DTR) Interrupt 1 Data Bit 1 Data Bit 1 Enable Interrupt RCVR Word Request Overrun Delta Bit 1 Bit 1 Bit 9 Transmitter ID FIFO Length to Send Error Data Holding Bit Reset Select (RTS) (OE) Set Register Bit 1 Ready Empty Interrupt 2 Data Bit 2 Data Bit 2 Enable Interrupt XMIT Number of Out 1 Parity Trailing Bit 2 Bit 2 Bit 10 Receiver ID FIFO Stop Bits Bit Error Edge Ring Line Status Bit Reset (Note 3) (PE) Indicator Interrupt 3 Data Bit 3 Data Bit 3 Enable Interrupt DMA Parity IRQ Framing Delta Bit 3 Bit 3 Bit 11 MODEM ID Mode Enable Enable Error Data Status Bit Select (FE) Carrier Interrupt (Note 2) Detect 4 Data Bit 4 Data Bit 4 0 0 Reserved Even Parity Loop Break Clear to Bit 4 Bit 4 Bit 12 Select Interrupt Send (BI) 5 Data Bit 5 Data Bit 5 0 0 Reserved Stick 0 Transmitter Data Bit 5 Bit 5 Bit 13 Parity Holding Set Register Ready (THRE) 6 Data Bit 6 Data Bit 6 0 FIFOs RCVR Set 0 Transmitter Ring Bit 6 Bit 6 Bit 14 Enabled Trigger Break Empty Indicator (Note 2) (LSB) (TEMT) 7 Data Bit 7 Data Bit 7 0 FIFOs RCVR Divisor 0 Error in Data Bit 7 Bit 7 Bit 15 Enabled Trigger Latch RCVR Carrier (Note 2) (MSB) Access Bit FIFO Detect (DLAB) (Note 2) Note 1 Bit 0 is the least significant bit It is the first bit serially transmitted or received Note 2 These bits are always 0 in the NS16450 Mode Note 3 This bit no longer has a pin associated with it 54 |
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