PC87311AVF datasheet(58/78 Pages) NSC

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60 Serial Ports (Continued)

TABLE 6-10 PC87312 Interrupt Control Functions

FIFO

Interrupt

Mode

Identification

Interrupt Set and Reset Functions

Only

Bit 3

Bit 2

Bit 1

Bit 0

Priority

Interrupt Type

Interrupt Source

Interrupt Reset Control

Level

None

Highest

Receiver Line

Overrun Error Parity Error

Reading the Line

Status

Framing Error or Break Interrupt

Status Register

Second

Received Data

Receiver Data Available

Read Receiver Buffer

Available

Second

Character

No Characters Have Been

Reading the Receiver

Timeout

Removed from or Input to the

Buffer Register

Indication

RCVR FIFO during the Last 4

Char Times and there is at

least 1 Char in it during this Time

Third

Transmitter

Transmitter Holding

Reading the IIR Register

Holding Register

(if Source of Interrupt) or

Empty

Writing the Transmitter

Holding Register

Fourth

MODEM Status

Clear to Send or Data Set

Reading the MODEM

Ready or Ring Indicator or

Status Register

Data Carrier Detect

Bit 1

This bit enables the Transmitter Holding Register

Empty Interrupt when set to logic 1

Bit 2

This bit enables the Receiver Line Status Interrupt

when set to logic 1

Bit 3

This bit enables the MODEM Status Interrupt

when set to logic 1

Bits 4 – 7

These four bits are always logic 0

638 MODEM Control Register (MCR)

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM) The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 6-7 and are described below

Bit 0

This bit controls the Data Terminal Ready (DTR)

output When bit 0 is set to a logic 1 the DTR

output is forced to a logic 0 When bit 0 is reset to

a logic 0 the DTR output is forced to a logic 1 In

Local Loopback Mode this bit controls bit 5 of the

MODEM Status Register

Note

The DTR and RTS output of the UART may be applied to

an EIA inverting line driver (such as the DS1488) to ob-

tain the proper polarity input at the MODEM or data set

Bit 1

This bit controls the Request to Send (RTS) out-

put Bit 1 affects the RTS output in a manner iden-

tical to that described above for bit 0 In Local

Loopback Mode this bit controls bit 4 of the MO-

DEM Status Register

Bit 2

This bit is the OUT1 bit It does not have an output

pin associated with it It can be written to and read

by the CPU In Local Loopback Mode this bit con-

trols bit 6 of the Modem Status Register

Bit 3

This bit enables the interrupt when set No exter-

nal pin is associated with this bit other than

IRQ34 In Local Loopback Mode this bit controls

bit 7 of the MODEM Status Register

Bit 4

This bit provides a Local loopback feature for diag-

nostic testing of the UART When bit 4 is set to

logic 1 the following occur the transmitter Serial

Output (SOUT) is set to the Marking (logic 1) state

the receiver Serial Input (SIN) is disconnected the

output of the Transmitter Shift Register is ‘‘looped

back’’ (connected) to the Receiver Shift Register

the four MODEM Control inputs (DSR CTS RI

and DCD) are disconnected and the DTR RTS

OUT1 IRQ ENABLE bits in MCR are internally

connected to DSR CTS RI and DCD in MSR re-

spectively The MODEM Control output pins are

forced to their high (inactive) states In the Loop-

back Mode data that is transmitted is immediately

received This feature allows the processor to veri-

fy the transmit-and-received-data paths of the seri-

al port

In the Loopback Mode the receiver and transmit-

ter interrupts are fully operational The MODEM

Status Interrupts are also operational but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register The IRQ3

and 4 pins will be TRI-STATE in the Loopback

Mode

Bits 5 – 7

These bits are permanently set to logic 0

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