PC87311AVF datasheet(57/78 Pages) NSC

57 / 78 page

60 Serial Ports (Continued)

set to a logic 1 when a character is transferred from the

Transmitter Holding Register into the Transmitter Shift Reg-

ister The bit is reset to logic 0 whenever the CPU loads the

Transmitter Holding Register In the FIFO mode this bit is

set when the XMIT FIFO is empty it is cleared when at least

1 byte is written to the XMIT FIFO

Bit 6

This bit is the Transmitter Empty (TEMT) indicator

Bit 6 is set to a logic 1 whenever the Transmitter

Holding Register (THR) and the Transmitter Shift

whenever either the THR or TSR contains a data

character In the FIFO mode this bit is set to one

whenever the transmitter FIFO and the shift register

are both empty

Bit 7

In the NS16450 Mode this is a 0 In the FIFO Mode

LSR7 is set when there is at least one parity error

framing error or break indication in the FIFO LSR7 is

cleared when the CPU reads the LSR if there are no

subsequent errors in the FIFO

Note

The Line Status Register is intended for read operations

only Writing to this register is not recommended as this

operation is only used for factory testing In the FIFO mode

the software must load a data byte in the Rx FIFO via the

Loopback Mode in order to write to LSR2–LSR4 LSR0 and

LSR7 can’t be written to in FIFO Mode

635 FIFO Control Register (FCR)

This is a write only register at the same location as the IIR

(the IIR is a read only register) This register is used to en-

able the FIFOs clear the FIFOs set the RCVR FIFO trigger

level and select the type of DMA signaling

Bit 0

Writinga1to FCR0 enables both the XMIT and

RCVR FIFOs Resetting FCR0 will clear all bytes in

both FIFOs When changing from FIFO Mode to

NS16450 Mode and vice versa data is automati-

cally cleared from the FIFOs This bit must be a 1

when other FCR bits are written to or they will not

be programmed

Bit 1

Writinga1to FCR1 clears all bytes in the RCVR

FIFO and resets its counter logic to 0 The shift

bit position is self-clearing

Bit 2

Writinga1to FCR2 clears all bytes in the XMIT

FIFO and resets its counter logic to 0 The shift

bit position is self-clearing

Bit 3

Writing to FCR3 causes no change in UART opera-

tions

NOTE THAT THE TXRDY AND RXRDY PINS ARE

NOT AVAILABLE IN THE PC87312

Bits 4 5

FCR4 to FCR5 are reserved for future use

Bits 6 7

FCR6 and FCR7 are used to designate the inter-

rupt trigger level When the number of bytes in the

RCVR FIFO equals the designated interrupt trigger

level a Received Data Available Interrupt is acti-

vated This interrupt must be enabled by setting

IER0

FCR Bits

RCVR FIFO

Trigger Level (Bytes)

636 Interrupt Identification Register (IIR)

In order to provide minimum software overhead during data

character transfers the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister The four levels of interrupt conditions in order of priori-

ty are Receiver Line Status Received Data Ready Trans-

mitter Holding Register Empty and MODEM Status

When the CPU accesses the IIR the UART freezes all inter-

rupts and indicates the highest priority pending interrupt to

the CPU While this CPU access is occurring the UART

records new interrupts but does not change its current indi-

cation until the current access is complete Table 6-2 shows

the contents of the IIR Details on each bit follow

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending

When bit 0 is a logic 0 an interrupt is pending and

the IIR contents may be used as a pointer to the

appropriate interrupt service routine When bit 0 is

a logic 1 no interrupt is pending

Bits 1 2

These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated in

Table 6-10

Bit 3

In the 16450 mode this bit is 0 In the FIFO mode

this bit is set along with bit 2 when a timeout inter-

rupt is pending

Bits 4 5

These bits of the IIR are always logic 0

Bits 6 7

These two bits are set when FCR0 e 1 (FIFO

Mode enabled)

637 Interrupt Enable Register (IER)

This register enables the five types of UART interrupts

Each interrupt can individually activate the appropriate inter-

rupt (IRQ3 or IRQ4) output signal It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER) Similarly setting bits of

this register to a logic 1 enables the selected interrupt(s)

Disabling an interrupt prevents it from being indicated as

active in the IIR and from activating the interrupt output sig-

nal All other system functions operate in their normal man-

ner including the setting of the Line Status and MODEM

Status Registers Table 6-7 shows the contents of the IER

Details on each bit follow See MODEM Control Register bit

3 for more information on enabling the interrupt pin

Bit 0

When set to logic 1 this bit enables the Received

Data Available Interrupt and Timeout Interrupt in

the FIFO Mode

PC87311AVF Datasheet(PDF) 57 Page - National Semiconductor (TI)

PC87311AVF Datasheet(HTML) 57 Page - National Semiconductor (TI)

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