SN65LVDS1, SN65LVDS2, SN65LVDT2

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SLLS373L – JULY 1999 – REVISED DECEMBER 2014

10.2.1.2.3

Driver Input Voltage

The SN65LVDS1 input is designed to support a wide input voltage range. The input stage can accept signals as

high as 5 V, independent of the supply voltage being used on the driver. This wide input range allows operation

with 3.3-V and 5-V sources. While the input stage does support this wide input range, the driver will operate with

a decision threshold of ~1.4 V. For LVTTL input signals, this threshold is well-matched to the voltages

representing HI and LO logic levels. For 5-V TTL input signals and CMOS input signals, this fixed threshold at

1.4 V will result in some duty-cycle distortion. The level of the distortion is easily calculated based upon the input

slew rate, as well as the signaling rate of the input data. Quite often this distortion is insignificant, although the

designer should consider this effect where the device is operated at higher speeds, or when duty-cycle is a

critical feature.

10.2.1.2.4

Driver Output Voltage

The SN65LVDS1 driver output is a 1.2-V common-mode voltage, with a nominal differential output signal of 350

voltage is twice this value, or 700 mV. As mentioned previously, the minimum differential output voltage is 200

mV when the supply voltage is between 2.4 V and 3 V. While 200 mV does not meet the minimum specified

voltage for an LVDS-compliant driver, the designer may choose to employ this driver with a lower supply voltage,

as long as attention is paid to the channel noise margin.

As we will see shortly, LVDS receiver thresholds are ±100 mV. With these receiver decision thresholds, it is clear

that the disadvantage of operating the driver with a lower supply will be noise margin. With fully compliant LVDS

drivers and receivers, we would expect a minimum of ~150 mV of noise margin (247-mV minimum output

voltage – 100-mV maximum input requirement). If we operate the SN65LVDS1 with a supply in the range of 2.4

V to 3 V, the minimum noise margin will drop to 100 mV (200 mV – 100 mV).

10.2.1.2.5

Interconnecting Media

The physical communication channel between the driver and the receiver may be any balanced paired metal

conductors meeting the requirements of the LVDS standard, the key points which will be included here. This

media may be a twisted pair, twinax, flat ribbon cable, or PCB traces.

The nominal characteristic impedance of the interconnect should be between 100

Ω and 120 Ω with variation no

more than 10% (90

Ω to 132 Ω).

10.2.1.2.6

PCB Transmission Lines

As per SNLA187, Figure 20 depicts several transmission line structures commonly used in printed-circuit boards

(PCBs). Each structure consists of a signal line and a return path with uniform cross-section along its length. A

microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a

ground or power plane. A stripline is a signal trace in the inner layer, with a dielectric layer in between a ground

plane above and below the signal trace. The dimensions of the structure along with the dielectric material

properties determine the characteristic impedance of the transmission line (also called controlled-impedance

transmission line).

When two signal lines are placed close by, they form a pair of coupled transmission lines. Figure 20 shows

examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. When excited by

differential signals, the coupled transmission line is referred to as a differential pair. The characteristic impedance

of each line is called odd-mode impedance. The sum of the odd-mode impedances of each line is the differential

impedance of the differential pair. In addition to the trace dimensions and dielectric material properties, the

spacing between the two traces determines the mutual coupling and impacts the differential impedance. When

the two lines are immediately adjacent; for example, S is less than 2W, the differential pair is called a tightly-

coupled differential pair. To maintain constant differential impedance along the length, it is important to keep the

trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines.

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