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SN65LVDT2DBVR Datasheet(PDF) 7 Page - Texas Instruments |
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SN65LVDT2DBVR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 42 page ![]() SN65LVDS1, SN65LVDS2, SN65LVDT2 www.ti.com SLLS373L – JULY 1999 – REVISED DECEMBER 2014 7.8 Receiver Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Propagation delay time, low-to-high- tPLH 1.4 2.6 3.6 ns level output Propagation delay time, high-to-low- tPHL 1.4 2.5 3.6 ns CL = 10 pF, See Figure 14 level output tsk(p) Pulse skew (|tpHL – tpLH|) (2) 0.1 0.6 ns tr Output signal rise time 0.8 1.4 ns tf Output signal fall time 0.8 1.4 ns VCC = 3.0 V – 3.6 V 2.2 3 5.5 V/ns tr(slew) Output slew rate (rising) VCC = 2.4 V – 2.7 V 1.5 1.9 2.9 V/ns CL = 10 pF VCC = 3.0 V – 3.6 V 2.7 3.8 6 V/ns tf(slew) Output slew rate (falling) VCC = 2.4 V – 2.7 V 2.1 2.3 3.9 V/ns (1) All typical values are at 25°C and with a 2.7-V supply. (2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 |
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