SN65LVDS1, SN65LVDS2, SN65LVDT2

www.ti.com

SLLS373L – JULY 1999 – REVISED DECEMBER 2014

Layout Guidelines (continued)

12.1.6 Decoupling

Each power or ground lead of a high-speed device should be connected to the PCB through a low inductance

path. For best results, one or more vias are used to connect a power or ground pin to the nearby plane. Ideally,

via placement is immediately adjacent to the pin to avoid adding trace inductance. Placing a power plane closer

to the top of the board reduces the effective via length and its associated inductance.

Figure 29. Low Inductance, High-Capacitance Power Connection

underneath the package to minimize the loop area. This extends the useful frequency range of the added

capacitance. Small-physical-size capacitors, such as 0402 or even 0201, or X7R surface-mount capacitors

should be used to minimize body inductance of capacitors. Each bypass capacitor is connected to the power and

ground plane through vias tangent to the pads of the capacitor as shown in Figure 30(a).

An X7R surface-mount capacitor of size 0402 has about 0.5 nH of body inductance. At frequencies above 30

MHz or so, X7R capacitors behave as low-impedance inductors. To extend the operating frequency range to a

few hundred MHz, an array of different capacitor values like 100 pF, 1 nF, 0.03

μF, and 0.1 μF are commonly

used in parallel. The most effective bypass capacitor can be built using sandwiched layers of power and ground

at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB.

Refer back to Figure 5-1 for some examples. Many high-speed devices provide a low-inductance GND

connection on the backside of the package. This center dap must be connected to a ground plane through an

array of vias. The via array reduces the effective inductance to ground and enhances the thermal performance of

the small Surface Mount Technology (SMT) package. Placing vias around the perimeter of the dap connection

ensures proper heat spreading and the lowest possible die temperature. Placing high-performance devices on

opposing sides of the PCB using two GND planes (as shown in Figure 20) creates multiple paths for heat

transfer. Often thermal PCB issues are the result of one device adding heat to another, resulting in a very high

local temperature. Multiple paths for heat transfer minimize this possibility. In many cases the GND dap that is so

important for heat dissipation makes the optimal decoupling layout impossible to achieve due to insufficient pad-

to-dap spacing as shown in Figure 30(b). When this occurs, placing the decoupling capacitor on the backside of

as possible while still allowing for sufficient solder mask coverage. If the via is left open, solder may flow from the

pad and into the via barrel. This will result in a poor solder connection.

Copyright © 1999–2014, Texas Instruments Incorporated

Submit Documentation Feedback

29

Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2