TAS5721 datasheet(36/78 Pages) TI1

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7-BitSlave Address

8-BitRegister Address(N)

8-BitRegisterDataFor

Address(N)

Start

Stop

SDA

SCL

8-BitRegisterDataFor

Address(N)

T0035-01

CH1_audio

CH2_audio

PWM1

PWM2

OFF3

OFF4

B0488-01

D (Off)

B (Off)

C (R–)

–

A (L+)

CH1_audio

PWM1

PWM3

OFF2

OFF4

B0488-02

–

D (Off)

B (Off)

C (L–)

A (L+)

TAS5721

SLOS739A – JULY 2012 – REVISED MARCH 2016

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Device Functional Modes (continued)

Table 1. Output Configuration Quick Reference (continued)

OUTPUT

CONFIGURATION

MODULATION MODE

BLOCK DIAGRAM

1.0 Mono PBTL

0x05[7] = 0

0x05[5] = 0

0x05[2] = 0

0x19[7:0] = 0x3A

0x1A[7:0] = 0x0F

0x20[23] = 0

0x20[15:12] = 0x7

0x25[23:8] = 0x0123

0x05[7] = 0

0x05[5] = 0

0x05[2] = 0

0x19[7:0] = 0x3A

0x1A[7:0] = 0x0A

0x20[23] = 1

0x20[15:12] = 0x7

0x25[23:8] = 0x0123

9.5 Programming

9.5.1 General I2C Operation

The I2C bus employs two signals to communicate between integrated circuits in a system: (data) SDA and (clock)

SCL. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-

bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A

high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit

transitions must occur within the low time of the clock period. These conditions are shown in Figure 67. The

master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS5721 holds SDA low during the acknowledge clock

period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.

Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the

same signals through a bidirectional bus using a wired-AND connection. An external pullup resistor must be used

for the SDA and SCL signals to set the high level for the bus.

Figure 67. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in Figure 67.

Pin ADR/FAULT defines the I2C device address. An external 15-k

Ω pull down on this pin gives a device address

of 0x34 and a 15-k

Ω pull up gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010

(0x34).

TAS5721 Datasheet(PDF) 36 Page - Texas Instruments

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