ST72344K2 datasheet(57/247 Pages) STMICROELECTRONICS

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ST72344xx, ST2345xx

Interrupts

Doc ID 12321 Rev 6

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Figure 23.

Nested interrupt management

8.5

Interrupt register description

8.5.1

CPU CC register interrupt bits

Reset value: 111x 1010 (xAh)

Bits 5, 3 = I1, I0 Software interrupt priority

These two bits indicate the current interrupt software priority.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is

given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and

PUSH/POP instructions (see Table 16: Dedicated interrupt instruction set).

MAIN

IT2

TRAP

MAIN

IT0

3/0

RIM

IT1

IT4

IT1

IT2

IT3

11 / 10

SOFTWARE

PRIORITY

LEVEL

Read/Write

Table 14.

Interrupt software priority

Priority

Level

Level 0 (main)

Low

High

Level 1

Level 2

Level 3 (= interrupt disable(1))

TRAP and reset events can interrupt a level 3 program.

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