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ST72344K2 Datasheet(PDF) 59 Page - STMicroelectronics |
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ST72344K2 Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 247 page ![]() ST72344xx, ST2345xx Interrupts Doc ID 12321 Rev 6 59/247 Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0 Table 16. Dedicated interrupt instruction set (continued) Instruction New description Function/example I1 H I0 N Z C Table 17. Interrupt mapping No. Source block Description Register label Priority order Exit from Halt (1) 1. Valid for Halt and Active-halt modes except for the MCC/RTC interrupt source which exits from Active-halt mode only and AWU interrupt which exits from AWUFH mode only. Address vector Reset Reset N/A Highest priority Lowest priority yes FFFEh-FFFFh TRAP/ICD Software or ICD interrupt no FFFCh-FFFDh 0 AWU Auto wakeup interrupt AWUCSR yes FFFAh-FFFBh 1 MCC/RTC RTC time base interrupt MCCSR yes FFF8h-FFF9h 2 ei0 External interrupt Port PA3, PE1 N/A yes FFF6h-FFF7h 3 ei1 External interrupt Port PF2:0 N/A yes FFF4h-FFF5h 4 ei2 External interrupt Port PB3:0 N/A yes FFF2h-FFF3h 5 ei3 External interrupt Port PB4 N/A yes FFF0h-FFF1h 6 I2C3SNS I2C3SNS address 3 interrupt I2C3SSR no FFEEh-FFEFh 7 I2C3SNS I2C3SNS address 1 & 2 interrupt no FFECh-FFEDh 8 SPI SPI peripheral interrupts SPISR yes(2) 2. Exit from Halt possible when SPI is in slave mode. FFEAh-FFEBh 9 TIMER A TIMER A peripheral interrupts TASR no FFE8h-FFE9h 10 TIMER B TIMER B peripheral interrupts TBSR no FFE6h-FFE7h 11 SCI SCI peripheral interrupt SCISR no FFE4h-FFE5h 12 AVD Auxiliary-voltage-detector interrupt SICSR no FFE2h-FFE3h 13 I2CI2C peripheral interrupt I2CSRx no FFE0h-FFE1h |
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