ST72344K2 datasheet(42/247 Pages) STMICROELECTRONICS

42 / 247 page

Supply, reset and clock management

ST72344xx, ST2345xx

42/247

Doc ID 12321 Rev 6

7.2

Phase locked loop

The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external

clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor

of 4 or 8 is selected by 3 option bits. Refer to Table 7 for the PLL configuration depending on

the required frequency and the application voltage. Refer to Section 15.1 for the option byte

description.

Figure 14.

PLL output frequency timing diagram

When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs

the clock after a delay of tSTARTUP.

When the PLL output signal reaches the operating frequency, the LOCKED bit in the

SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of

tSTAB (see Figure 14).

Refer to Section 7.6.5: Register description for a description of the LOCKED bit in the

SICSR register.

Caution:

The PLL is not recommended for applications where timing accuracy is required.

Caution:

When the RC oscillator and the PLL are enabled, it is recommended to calibrate this clock

through the RCCRH and RCCRL registers.

Table 7.

PLL configurations

Target ratio

VDD

PLL ratio

DIV2

x4(1)

For a target ratio of x4 between 3.3 V - 3.65 V, this is the recommended configuration.

2.7 V - 3.65 V

OFF

3.3 V - 5.5 V

OFF

4/8 x

freq.

LOCKED bit set

tSTAB

tLOCK

input

tSTARTUP

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