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ST72344K2 Datasheet(PDF) 66 Page - STMicroelectronics |
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ST72344K2 Datasheet(HTML) 66 Page - STMicroelectronics |
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66 / 247 page ![]() Power-saving modes ST72344xx, ST2345xx 66/247 Doc ID 12321 Rev 6 Figure 27. Wait mode flowchart Note: Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 9.4 Halt mode The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Section 11.2: Main clock controller with real-time clock and beeper (MCC/RTC) for more details on the MCCSR register) and when the AWUEN bit in the AWUCSR register is cleared. The MCU can exit Halt mode on reception of either a specific interrupt (see Table 17: Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 29). When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog WFI INSTRUCTION RESET INTERRUPT Y N N Y CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF 10 ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX (1) ON 256 OR 4096 CPU CLOCK CYCLE DELAY |
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