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ST72325AR7-Auto Datasheet(PDF) 173 Page - STMicroelectronics

Part # ST72325AR7-Auto
Description  SCI asynchronous serial interface
PDF  243 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72325AR7-Auto Datasheet(HTML) 173 Page - STMicroelectronics

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ST72325xxx-Auto
I2C bus interface (I2C)
Doc ID 13770 Rev 3
173/243
16.7.5
I2C data register (DR)
16.7.6
I2C own address register (OAR1)
6:0
CC[6:0]
7-bit clock divider
These bits select the speed of the bus (fSCL) depending on the I
2C mode. They are
not cleared when the interface is disabled (PE = 0).
Refer to Section 19: Electrical characteristics for the table of values.
Note: The programmed fSCL assumes no load on SCL and SDA lines.
Table 87.
CCR register description (continued)
Bit
Name
Function
DR
Reset value: 0000 0000 (00h)
76
543
21
0
D[7:0]
RW
Table 88.
DR register description
Bit
Name
Function
7:0
D[7:0]
8-bit Data Register
These bits contain the byte to be received or transmitted on the bus.
Transmitter mode: Byte transmission start automatically when the software writes
in the DR register.
Receiver mode: The first data byte is received automatically in the DR register
using the least significant bit of the address.
Then, the following data bytes are received one by one after reading the DR
register.
OAR1
Reset value: 0000 0000 (00h)
76
543
21
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
RW
RW
RW
RW
RW
RW
RW
RW



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