ST72325AR7-Auto datasheet(170/243 Pages) STMICROELECTRONICS

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I2C bus interface (I2C)

ST72325xxx-Auto

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Doc ID 13770 Rev 3

ADD10

10-bit addressing in Master mode

This bit is set by hardware when the master has sent the first byte in 10-bit address

mode. It is cleared by software reading SR2 register followed by a write in the DR

peripheral is disabled (PE = 0).

0: No ADD10 event occurred.

1: Master has sent first address byte (header)

5TRA

Transmitter/Receiver

When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared

automatically when BTF is cleared. It is also cleared by hardware after detection of

Stop condition (STOPF = 1), loss of bus arbitration (ARLO = 1) or when the

interface is disabled (PE = 0).

0: Data byte received (if BTF = 1)

1: Data byte transmitted

4BUSY

Bus busy

This bit is set by hardware on detection of a Start condition and cleared by hardware

on detection of a Stop condition. It indicates a communication in progress on the

bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.

0: No communication on the bus

1: Communication ongoing on the bus

Note: The BUSY flag is NOT updated when the interface is disabled (PE = 0). This

can have consequences when operating in Multimaster mode; that is, a second

active I2C master commencing a transfer with an unset BUSY bit can cause a

conflict resulting in lost data. A software workaround consists of checking that the

I2C is not busy before enabling the I2C Multimaster cell.

3BTF

Byte transfer finished

This bit is set by hardware as soon as a byte is correctly received or transmitted with

interrupt generation if ITE = 1. It is cleared by software reading SR1 register

followed by a read or write of DR register. It is also cleared by hardware when the

interface is disabled (PE = 0).

Following a byte transmission, this bit is set after reception of the acknowledge clock

pulse. In case an address byte is sent, this bit is set only after the EV6 event (see

Figure 70). BTF is cleared by reading SR1 register followed by writing the next byte

in DR register.

Following a byte reception, this bit is set after transmission of the acknowledge clock

pulse if ACK = 1. BTF is cleared by reading SR1 register followed by reading the

byte from DR register.

The SCL line is held low while BTF = 1.

0: Byte transfer not done

1: Byte transfer succeeded

2ADSL

Address matched (Slave mode)

This bit is set by hardware as soon as the received slave address matched with the

OAR register content or a general call is recognized. An interrupt is generated if

ITE = 1. It is cleared by software reading SR1 register or by hardware when the

interface is disabled (PE = 0).

The SCL line is held low while ADSL = 1.

0: Address mismatched or not received

1: Received address matched

Table 85.

SR1 register description (continued)

Bit

Name

Function

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