ST72325AR7-Auto datasheet(168/243 Pages) STMICROELECTRONICS

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I2C bus interface (I2C)

ST72325xxx-Auto

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Doc ID 13770 Rev 3

16.7

16.7.1

I2C control register (CR)

Reset value: 0000 0000 (00h)

543

Reserved

ENGC

START

ACK

STOP

ITE

RWRW

Table 84.

CR register description

Bit

Name

Function

7:6

Reserved. Forced to 0 by hardware.

5PE

Peripheral enable

This bit is set and cleared by software.

0: Peripheral disabled

1: Master/Slave capability

Notes:

- When PE = 0, all the bits of the CR register and the SR register except the Stop

bit are reset. All outputs are released while PE = 0

- When PE = 1, the corresponding I/O pins are selected by hardware as alternate

functions.

To enable the I2C interface, write the CR register TWICE with PE = 1 as the first

write only activates the interface (only PE is set).

4ENGC

Enable General Call

This bit is set and cleared by software. It is also cleared by hardware when the

interface is disabled (PE = 0). The 00h General Call address is acknowledged (01h

ignored).

0: General Call disabled

1: General Call enabled

Note: In accordance with the I2C standard, when GCAL addressing is enabled, an

I2C slave can only receive data. It will not transmit data to the master.

3START

Generation of a Start condition

This bit is set and cleared by software. It is also cleared by hardware when the

interface is disabled (PE = 0) or when the Start condition is sent (with interrupt

generation if ITE = 1).

In Master mode

0: No start generation

1: Repeated start generation

In Slave mode

0: No start generation

1: Start generation when the bus is free

2ACK

Acknowledge enable

This bit is set and cleared by software. It is also cleared by hardware when the

interface is disabled (PE = 0).

0: No acknowledge returned

1: Acknowledge returned after an address byte or a data byte is received

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